radeon.h

U-boot源码 ARM7启动代码

#define PPLL_ATOMIC_UPDATE_R		0x00008000
#define PPLL_ATOMIC_UPDATE_W		0x00008000
#define PPLL_VGA_ATOMIC_UPDATE_EN	0x00020000
#define R300_PPLL_REF_DIV_ACC_MASK	(0x3ff << 18)
#define R300_PPLL_REF_DIV_ACC_SHIFT	18

#define GUI_ACTIVE			0x80000000


#define MC_IND_INDEX			0x01F8
#define MC_IND_DATA			0x01FC

/* PAD_CTLR_STRENGTH */
#define PAD_MANUAL_OVERRIDE		0x80000000

/* pllCLK_PIN_CNTL */
#define CLK_PIN_CNTL__OSC_EN_MASK			0x00000001L
#define CLK_PIN_CNTL__OSC_EN				0x00000001L
#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK			0x00000004L
#define CLK_PIN_CNTL__XTL_LOW_GAIN			0x00000004L
#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK		0x00000010L
#define CLK_PIN_CNTL__DONT_USE_XTALIN			0x00000010L
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK		0x00000020L
#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE			0x00000020L
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK		0x00000800L
#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN			0x00000800L
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK	0x00001000L
#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN		0x00001000L
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK	0x00002000L
#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND		0x00002000L
#define CLK_PIN_CNTL__CG_SPARE_MASK			0x00004000L
#define CLK_PIN_CNTL__CG_SPARE				0x00004000L
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK		0x00008000L
#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL		0x00008000L
#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK		0x00010000L
#define CLK_PIN_CNTL__CP_CLK_RUNNING			0x00010000L
#define CLK_PIN_CNTL__CG_SPARE_RD_MASK			0x00060000L
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK		0x00080000L
#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb			0x00080000L
#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK			0xff000000L

/* pllCLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT		0x00000000
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT		0x00000001
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT		0x00000002
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT	0x00000003
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT		0x00000004
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT		0x00000005
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT		0x00000006
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT		0x00000007
#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT		0x00000008
#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT		0x00000009
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT		0x0000000a
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT	0x0000000c
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT		0x0000000d
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT	0x0000000f
#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT			0x00000010
#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT		0x00000011
#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT		0x00000012
#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT		0x00000013
#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT			0x00000014
#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT		0x00000015
#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT		0x00000018
#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT	0x0000001e
#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT		0x0000001f

/* pllP2PLL_CNTL */
#define P2PLL_CNTL__P2PLL_RESET_MASK			0x00000001L
#define P2PLL_CNTL__P2PLL_RESET				0x00000001L
#define P2PLL_CNTL__P2PLL_SLEEP_MASK			0x00000002L
#define P2PLL_CNTL__P2PLL_SLEEP				0x00000002L
#define P2PLL_CNTL__P2PLL_TST_EN_MASK			0x00000004L
#define P2PLL_CNTL__P2PLL_TST_EN			0x00000004L
#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK		0x00000010L
#define P2PLL_CNTL__P2PLL_REFCLK_SEL			0x00000010L
#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK		0x00000020L
#define P2PLL_CNTL__P2PLL_FBCLK_SEL			0x00000020L
#define P2PLL_CNTL__P2PLL_TCPOFF_MASK			0x00000040L
#define P2PLL_CNTL__P2PLL_TCPOFF			0x00000040L
#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK			0x00000080L
#define P2PLL_CNTL__P2PLL_TVCOMAX			0x00000080L
#define P2PLL_CNTL__P2PLL_PCP_MASK			0x00000700L
#define P2PLL_CNTL__P2PLL_PVG_MASK			0x00003800L
#define P2PLL_CNTL__P2PLL_PDC_MASK			0x0000c000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK		0x00010000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN		0x00010000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK	0x00040000L
#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC		0x00040000L
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK	0x00080000L
#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET		0x00080000L

/* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT		0x00000000
#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT		0x00000004
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT		0x00000005
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT		0x00000006
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT	0x00000007
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT		0x00000008
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT	0x0000000b
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT	0x0000000c
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT	0x0000000d
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT	0x0000000e
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT	0x0000000f


/* pllPIXCLKS_CNTL */
#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK		0x00000003L
#define PIXCLKS_CNTL__PIX2CLK_INVERT			0x00000010L
#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT		0x00000020L
#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb		0x00000040L
#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb		0x00000080L
#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL			0x00000100L
#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb		0x00000800L
#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb		0x00001000L
#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb	0x00002000L
#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb		0x00004000L
#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb		0x00008000L
#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb	(1 << 9)
#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb		(1 << 10)
#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb	(1 << 13)
#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb	(1 << 16)
#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb	(1 << 17)
#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb		(1 << 18)
#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb	(1 << 19)
#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)


/* pllP2PLL_DIV_0 */
#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK			0x000007ffL
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK		0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W		0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK		0x00008000L
#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R		0x00008000L
#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK		0x00070000L

/* pllSCLK_CNTL */
#define SCLK_CNTL__SCLK_SRC_SEL_MASK			0x00000007L
#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT			0x00000008L
#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT			0x00000010L
#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT			0x00000020L
#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT			0x00000040L
#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT			0x00000080L
#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT		0x00000100L
#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT			0x00000200L
#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT			0x00000400L
#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT			0x00000800L
#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT			0x00001000L
#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT			0x00002000L
#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT			0x00004000L
#define SCLK_CNTL__DYN_STOP_LAT_MASK			0x00007ff8
#define SCLK_CNTL__FORCE_DISP2				0x00008000L
#define SCLK_CNTL__FORCE_CP				0x00010000L
#define SCLK_CNTL__FORCE_HDP				0x00020000L
#define SCLK_CNTL__FORCE_DISP1				0x00040000L
#define SCLK_CNTL__FORCE_TOP				0x00080000L
#define SCLK_CNTL__FORCE_E2				0x00100000L
#define SCLK_CNTL__FORCE_SE				0x00200000L
#define SCLK_CNTL__FORCE_IDCT				0x00400000L
#define SCLK_CNTL__FORCE_VIP				0x00800000L
#define SCLK_CNTL__FORCE_RE				0x01000000L
#define SCLK_CNTL__FORCE_PB				0x02000000L
#define SCLK_CNTL__FORCE_TAM				0x04000000L
#define SCLK_CNTL__FORCE_TDM				0x08000000L
#define SCLK_CNTL__FORCE_RB				0x10000000L
#define SCLK_CNTL__FORCE_TV_SCLK			0x20000000L
#define SCLK_CNTL__FORCE_SUBPIC				0x40000000L
#define SCLK_CNTL__FORCE_OV0				0x80000000L
#define SCLK_CNTL__R300_FORCE_VAP			(1<<21)
#define SCLK_CNTL__R300_FORCE_SR			(1<<25)
#define SCLK_CNTL__R300_FORCE_PX			(1<<26)
#define SCLK_CNTL__R300_FORCE_TX			(1<<27)
#define SCLK_CNTL__R300_FORCE_US			(1<<28)
#define SCLK_CNTL__R300_FORCE_SU			(1<<30)
#define SCLK_CNTL__FORCEON_MASK				0xffff8000L

/* pllSCLK_CNTL2 */
#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT		(1<<10)
#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT		(1<<11)
#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT		(1<<12)
#define SCLK_CNTL2__R300_FORCE_TCL			(1<<13)
#define SCLK_CNTL2__R300_FORCE_CBA			(1<<14)
#define SCLK_CNTL2__R300_FORCE_GA			(1<<15)

/* SCLK_MORE_CNTL */
#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT	0x00000001L
#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT		0x00000002L
#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT	0x00000004L
#define SCLK_MORE_CNTL__FORCE_DISPREGS			0x00000100L
#define SCLK_MORE_CNTL__FORCE_MC_GUI			0x00000200L
#define SCLK_MORE_CNTL__FORCE_MC_HOST			0x00000400L
#define SCLK_MORE_CNTL__STOP_SCLK_EN			0x00001000L
#define SCLK_MORE_CNTL__STOP_SCLK_A			0x00002000L
#define SCLK_MORE_CNTL__STOP_SCLK_B			0x00004000L
#define SCLK_MORE_CNTL__STOP_SCLK_C			0x00008000L
#define SCLK_MORE_CNTL__HALF_SPEED_SCLK			0x00010000L
#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP		0x00020000L
#define SCLK_MORE_CNTL__TVFB_SOFT_RESET			0x00040000L
#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC		0x00080000L
#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK		0x00400000L
#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK		0x00800000L
#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK		0xff000000L
#define SCLK_MORE_CNTL__FORCEON				0x00000700L

/* MCLK_CNTL */
#define MCLK_CNTL__MCLKA_SRC_SEL_MASK			0x00000007L
#define MCLK_CNTL__YCLKA_SRC_SEL_MASK			0x00000070L
#define MCLK_CNTL__MCLKB_SRC_SEL_MASK			0x00000700L
#define MCLK_CNTL__YCLKB_SRC_SEL_MASK			0x00007000L
#define MCLK_CNTL__FORCE_MCLKA_MASK			0x00010000L
#define MCLK_CNTL__FORCE_MCLKA				0x00010000L
#define MCLK_CNTL__FORCE_MCLKB_MASK			0x00020000L
#define MCLK_CNTL__FORCE_MCLKB				0x00020000L
#define MCLK_CNTL__FORCE_YCLKA_MASK			0x00040000L
#define MCLK_CNTL__FORCE_YCLKA				0x00040000L
#define MCLK_CNTL__FORCE_YCLKB_MASK			0x00080000L
#define MCLK_CNTL__FORCE_YCLKB				0x00080000L
#define MCLK_CNTL__FORCE_MC_MASK			0x00100000L
#define MCLK_CNTL__FORCE_MC				0x00100000L
#define MCLK_CNTL__FORCE_AIC_MASK			0x00200000L
#define MCLK_CNTL__FORCE_AIC				0x00200000L
#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK			0x03000000L
#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK			0x0c000000L
#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK			0x30000000L
#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK			0xc0000000L
#define MCLK_CNTL__R300_DISABLE_MC_MCLKA		(1 << 21)
#define MCLK_CNTL__R300_DISABLE_MC_MCLKB		(1 << 21)

/* MCLK_MISC */
#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK	0x00000003L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK		0x00000004L
#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL		0x00000004L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK		0x00000008L
#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL		0x00000008L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK	0x00000010L
#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN		0x00000010L
#define MCLK_MISC__DLL_READY_LAT_MASK			0x00000100L
#define MCLK_MISC__DLL_READY_LAT			0x00000100L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK	0x00001000L
#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT		0x00001000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK	0x00002000L
#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT		0x00002000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK		0x00004000L
#define MCLK_MISC__MC_MCLK_DYN_ENABLE			0x00004000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK		0x00008000L
#define MCLK_MISC__IO_MCLK_DYN_ENABLE			0x00008000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK		0x00010000L
#define MCLK_MISC__CGM_CLK_TO_OUTPIN			0x00010000L
#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK		0x00020000L
#define MCLK_MISC__CLK_OR_COUNT_SEL			0x00020000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK	0x00040000L
#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND		0x00040000L
#define MCLK_MISC__CGM_SPARE_RD_MASK			0x00300000L
#define MCLK_MISC__CGM_SPARE_A_RD_MASK			0x00c00000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK		0x01000000L
#define MCLK_MISC__TCLK_TO_YCLKB_EN			0x01000000L
#define MCLK_MISC__CGM_SPARE_A_MASK			0x0e000000L

/* VCLK_ECP_CNTL */
#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK		0x00000003L
#define VCLK_ECP_CNTL__VCLK_INVERT			0x00000010L
#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT		0x00000020L
#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb		0x00000040L
#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb		0x00000080L
#define VCLK_ECP_CNTL__ECP_DIV_MASK			0x00000300L
#define VCLK_ECP_CNTL__ECP_FORCE_ON			0x00040000L
#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON			0x00080000L
#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)

/* PLL_PWRMGT_CNTL */
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK		0x00000001L
#define PLL_PWRMGT_CNTL__MPLL_TURNOFF			0x00000001L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK		0x00000002L
#define PLL_PWRMGT_CNTL__SPLL_TURNOFF			0x00000002L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK		0x00000004L
#define PLL_PWRMGT_CNTL__PPLL_TURNOFF			0x00000004L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK		0x00000008L
#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF			0x00000008L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK		0x00000010L
#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF			0x00000010L
#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK	0x000001e0L
#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK		0x00000600L
#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK		0x00001800L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK		0x00002000L
#define PLL_PWRMGT_CNTL__PM_MODE_SEL			0x00002000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK	0x00004000L
#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND		0x00004000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK	0x00008000L
#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND		0x00008000L
#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK			0x00010000L
#define PLL_PWRMGT_CNTL__MOBILE_SU			0x00010000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK		0x00020000L
#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK		0x00020000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK		0x00040000L
#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK		0x00040000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK	0x00080000L
#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE		0x00080000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK	0x00100000L
#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE		0x00100000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK	0x00200000L
#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD		0x00200000L
#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK		0xff000000L

/* CLK_PWRMGT_CNTL */
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK		0x00000001L
#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF		0x00000001L
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK		0x00000002L
#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF		0x00000002L
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK		0x00000004L
#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF		0x00000004L
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK		0x00000008L
#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF		0x00000008L
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK		0x00000010L
#define CLK_PWRMGT_CNTL__MCLK_TURNOFF			0x00000010L
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK		0x00000020L
#define CLK_PWRMGT_CNTL__SCLK_TURNOFF			0x00000020L
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK		0x00000040L
#define CLK_PWRMGT_CNTL__PCLK_TURNOFF			0x00000040L
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK		0x00000080L
#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF			0x00000080L
#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK		0x00000100L
#define CLK_PWRMGT_CNTL__MC_CH_MODE			0x00000100L
#define CLK_PWRMGT_CNTL__TEST_MODE_MASK			0x00000200L
#define CLK_PWRMGT_CNTL__TEST_MODE			0x00000200L
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK		0x00000400L
#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN			0x00000400L
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK	0x00001000L
#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE		0x00001000L
#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK		0x00006000L
#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK		0x00008000L