radeon.h

U-boot源码 ARM7启动代码

#define SCRATCH_ADDR			0x0774
#define DP_BRUSH_FRGD_CLR		0x147C
#define DP_BRUSH_BKGD_CLR		0x1478
#define DST_LINE_START			0x1600
#define DST_LINE_END			0x1604
#define SRC_OFFSET			0x15AC
#define SRC_PITCH			0x15B0
#define SRC_TILE			0x1704
#define SRC_PITCH_OFFSET		0x1428
#define SRC_X				0x1414
#define SRC_Y				0x1418
#define SRC_X_Y				0x1590
#define SRC_Y_X				0x1434
#define DST_Y_X				0x1438
#define DST_WIDTH_HEIGHT		0x1598
#define DST_HEIGHT_WIDTH		0x143c
#define DST_OFFSET			0x1404
#define SRC_CLUT_ADDRESS		0x1780
#define SRC_CLUT_DATA			0x1784
#define SRC_CLUT_DATA_RD		0x1788
#define HOST_DATA0			0x17C0
#define HOST_DATA1			0x17C4
#define HOST_DATA2			0x17C8
#define HOST_DATA3			0x17CC
#define HOST_DATA4			0x17D0
#define HOST_DATA5			0x17D4
#define HOST_DATA6			0x17D8
#define HOST_DATA7			0x17DC
#define HOST_DATA_LAST			0x17E0
#define DP_SRC_ENDIAN			0x15D4
#define DP_SRC_FRGD_CLR			0x15D8
#define DP_SRC_BKGD_CLR			0x15DC
#define SC_LEFT				0x1640
#define SC_RIGHT			0x1644
#define SC_TOP				0x1648
#define SC_BOTTOM			0x164C
#define SRC_SC_RIGHT			0x1654
#define SRC_SC_BOTTOM			0x165C
#define DP_CNTL				0x16C0
#define DP_CNTL_XDIR_YDIR_YMAJOR	0x16D0
#define DP_DATATYPE			0x16C4
#define DP_MIX				0x16C8
#define DP_WRITE_MSK			0x16CC
#define DP_XOP				0x17F8
#define CLR_CMP_CLR_SRC			0x15C4
#define CLR_CMP_CLR_DST			0x15C8
#define CLR_CMP_CNTL			0x15C0
#define CLR_CMP_MSK			0x15CC
#define DSTCACHE_MODE			0x1710
#define DSTCACHE_CTLSTAT		0x1714
#define DEFAULT_PITCH_OFFSET		0x16E0
#define DEFAULT_SC_BOTTOM_RIGHT		0x16E8
#define DEFAULT_SC_TOP_LEFT		0x16EC
#define SRC_PITCH_OFFSET		0x1428
#define DST_PITCH_OFFSET		0x142C
#define DP_GUI_MASTER_CNTL		0x146C
#define SC_TOP_LEFT			0x16EC
#define SC_BOTTOM_RIGHT			0x16F0
#define SRC_SC_BOTTOM_RIGHT		0x16F4
#define RB2D_DSTCACHE_MODE		0x3428
#define RB2D_DSTCACHE_CTLSTAT		0x342C
#define LVDS_GEN_CNTL			0x02d0
#define LVDS_PLL_CNTL			0x02d4
#define FP2_GEN_CNTL			0x0288
#define TMDS_CNTL			0x0294
#define TMDS_CRC			0x02a0
#define TMDS_TRANSMITTER_CNTL		0x02a4
#define MPP_TB_CONFIG			0x01c0
#define PAMAC0_DLY_CNTL			0x0a94
#define PAMAC1_DLY_CNTL			0x0a98
#define PAMAC2_DLY_CNTL			0x0a9c
#define FW_CNTL				0x0118
#define FCP_CNTL			0x0910
#define VGA_DDA_ON_OFF			0x02ec
#define TV_MASTER_CNTL			0x0800

/* #define BASE_CODE			0x0f0b */
#define BIOS_0_SCRATCH			0x0010
#define BIOS_1_SCRATCH			0x0014
#define BIOS_2_SCRATCH			0x0018
#define BIOS_3_SCRATCH			0x001c
#define BIOS_4_SCRATCH			0x0020
#define BIOS_5_SCRATCH			0x0024
#define BIOS_6_SCRATCH			0x0028
#define BIOS_7_SCRATCH			0x002c

#define HDP_SOFT_RESET			(1 << 26)

#define TV_DAC_CNTL			0x088c
#define GPIOPAD_MASK			0x0198
#define GPIOPAD_A			0x019c
#define GPIOPAD_EN			0x01a0
#define GPIOPAD_Y			0x01a4
#define ZV_LCDPAD_MASK			0x01a8
#define ZV_LCDPAD_A			0x01ac
#define ZV_LCDPAD_EN			0x01b0
#define ZV_LCDPAD_Y			0x01b4

/* PLL Registers */
#define CLK_PIN_CNTL			0x0001
#define PPLL_CNTL			0x0002
#define PPLL_REF_DIV			0x0003
#define PPLL_DIV_0			0x0004
#define PPLL_DIV_1			0x0005
#define PPLL_DIV_2			0x0006
#define PPLL_DIV_3			0x0007
#define VCLK_ECP_CNTL			0x0008
#define HTOTAL_CNTL			0x0009
#define M_SPLL_REF_FB_DIV		0x000a
#define AGP_PLL_CNTL			0x000b
#define SPLL_CNTL			0x000c
#define SCLK_CNTL			0x000d
#define MPLL_CNTL			0x000e
#define MDLL_CKO			0x000f
#define MDLL_RDCKA			0x0010
#define MCLK_CNTL			0x0012
#define AGP_PLL_CNTL			0x000b
#define PLL_TEST_CNTL			0x0013
#define CLK_PWRMGT_CNTL			0x0014
#define PLL_PWRMGT_CNTL			0x0015
#define MCLK_MISC			0x001f
#define P2PLL_CNTL			0x002a
#define P2PLL_REF_DIV			0x002b
#define PIXCLKS_CNTL			0x002d
#define SCLK_MORE_CNTL			0x0035

/* MCLK_CNTL bit constants */
#define FORCEON_MCLKA			(1 << 16)
#define FORCEON_MCLKB			(1 << 17)
#define FORCEON_YCLKA			(1 << 18)
#define FORCEON_YCLKB			(1 << 19)
#define FORCEON_MC			(1 << 20)
#define FORCEON_AIC			(1 << 21)

/* SCLK_CNTL bit constants */
#define DYN_STOP_LAT_MASK		0x00007ff8
#define CP_MAX_DYN_STOP_LAT		0x0008
#define SCLK_FORCEON_MASK		0xffff8000

/* SCLK_MORE_CNTL bit constants */
#define SCLK_MORE_FORCEON		0x0700

/* BUS_CNTL bit constants */
#define BUS_DBL_RESYNC			0x00000001
#define BUS_MSTR_RESET			0x00000002
#define BUS_FLUSH_BUF			0x00000004
#define BUS_STOP_REQ_DIS		0x00000008
#define BUS_ROTATION_DIS		0x00000010
#define BUS_MASTER_DIS			0x00000040
#define BUS_ROM_WRT_EN			0x00000080
#define BUS_DIS_ROM			0x00001000
#define BUS_PCI_READ_RETRY_EN		0x00002000
#define BUS_AGP_AD_STEPPING_EN		0x00004000
#define BUS_PCI_WRT_RETRY_EN		0x00008000
#define BUS_MSTR_RD_MULT		0x00100000
#define BUS_MSTR_RD_LINE		0x00200000
#define BUS_SUSPEND			0x00400000
#define LAT_16X				0x00800000
#define BUS_RD_DISCARD_EN		0x01000000
#define BUS_RD_ABORT_EN			0x02000000
#define BUS_MSTR_WS			0x04000000
#define BUS_PARKING_DIS			0x08000000
#define BUS_MSTR_DISCONNECT_EN		0x10000000
#define BUS_WRT_BURST			0x20000000
#define BUS_READ_BURST			0x40000000
#define BUS_RDY_READ_DLY		0x80000000

/* PIXCLKS_CNTL */
#define PIX2CLK_SRC_SEL_MASK		0x03
#define PIX2CLK_SRC_SEL_CPUCLK		0x00
#define PIX2CLK_SRC_SEL_PSCANCLK	0x01
#define PIX2CLK_SRC_SEL_BYTECLK		0x02
#define PIX2CLK_SRC_SEL_P2PLLCLK	0x03
#define PIX2CLK_ALWAYS_ONb		(1<<6)
#define PIX2CLK_DAC_ALWAYS_ONb		(1<<7)
#define PIXCLK_TV_SRC_SEL		(1 << 8)
#define PIXCLK_LVDS_ALWAYS_ONb		(1 << 14)
#define PIXCLK_TMDS_ALWAYS_ONb		(1 << 15)


/* CLOCK_CNTL_INDEX bit constants */
#define PLL_WR_EN			0x00000080

/* CONFIG_CNTL bit constants */
#define CFG_VGA_RAM_EN			0x00000100
#define CFG_ATI_REV_ID_MASK		(0xf << 16)
#define CFG_ATI_REV_A11			(0 << 16)
#define CFG_ATI_REV_A12			(1 << 16)
#define CFG_ATI_REV_A13			(2 << 16)

/* CRTC_EXT_CNTL bit constants */
#define VGA_ATI_LINEAR			0x00000008
#define VGA_128KAP_PAGING		0x00000010
#define XCRT_CNT_EN			(1 << 6)
#define CRTC_HSYNC_DIS			(1 << 8)
#define CRTC_VSYNC_DIS			(1 << 9)
#define CRTC_DISPLAY_DIS		(1 << 10)
#define CRTC_CRT_ON			(1 << 15)


/* DSTCACHE_CTLSTAT bit constants */
#define RB2D_DC_FLUSH			(3 << 0)
#define RB2D_DC_FLUSH_ALL		0xf
#define RB2D_DC_BUSY			(1 << 31)


/* CRTC_GEN_CNTL bit constants */
#define CRTC_DBL_SCAN_EN		0x00000001
#define CRTC_CUR_EN			0x00010000
#define CRTC_INTERLACE_EN		(1 << 1)
#define CRTC_BYPASS_LUT_EN		(1 << 14)
#define CRTC_EXT_DISP_EN		(1 << 24)
#define CRTC_EN				(1 << 25)
#define CRTC_DISP_REQ_EN_B		(1 << 26)

/* CRTC_STATUS bit constants */
#define CRTC_VBLANK			0x00000001

/* CRTC2_GEN_CNTL bit constants */
#define CRT2_ON				(1 << 7)
#define CRTC2_DISPLAY_DIS		(1 << 23)
#define CRTC2_EN			(1 << 25)
#define CRTC2_DISP_REQ_EN_B		(1 << 26)

/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
#define CUR_LOCK			0x80000000

/* GPIO bit constants */
#define GPIO_A_0			(1 <<  0)
#define GPIO_A_1			(1 <<  1)
#define GPIO_Y_0			(1 <<  8)
#define GPIO_Y_1			(1 <<  9)
#define GPIO_EN_0			(1 << 16)
#define GPIO_EN_1			(1 << 17)
#define GPIO_MASK_0			(1 << 24)
#define GPIO_MASK_1			(1 << 25)
#define VGA_DDC_DATA_OUTPUT		GPIO_A_0
#define VGA_DDC_CLK_OUTPUT		GPIO_A_1
#define VGA_DDC_DATA_INPUT		GPIO_Y_0
#define VGA_DDC_CLK_INPUT		GPIO_Y_1
#define VGA_DDC_DATA_OUT_EN		GPIO_EN_0
#define VGA_DDC_CLK_OUT_EN		GPIO_EN_1


/* FP bit constants */
#define FP_CRTC_H_TOTAL_MASK		000003ff
#define FP_CRTC_H_DISP_MASK		0x01ff0000
#define FP_CRTC_V_TOTAL_MASK		0x00000fff
#define FP_CRTC_V_DISP_MASK		0x0fff0000
#define FP_H_SYNC_STRT_CHAR_MASK	0x00001ff8
#define FP_H_SYNC_WID_MASK		0x003f0000
#define FP_V_SYNC_STRT_MASK		0x00000fff
#define FP_V_SYNC_WID_MASK		0x001f0000
#define FP_CRTC_H_TOTAL_SHIFT		0x00000000
#define FP_CRTC_H_DISP_SHIFT		0x00000010
#define FP_CRTC_V_TOTAL_SHIFT		0x00000000
#define FP_CRTC_V_DISP_SHIFT		0x00000010
#define FP_H_SYNC_STRT_CHAR_SHIFT	0x00000003
#define FP_H_SYNC_WID_SHIFT		0x00000010
#define FP_V_SYNC_STRT_SHIFT		0x00000000
#define FP_V_SYNC_WID_SHIFT		0x00000010

/* FP_GEN_CNTL bit constants */
#define FP_FPON				(1 << 0)
#define FP_TMDS_EN			(1 << 2)
#define FP_PANEL_FORMAT			(1 << 3)
#define FP_EN_TMDS			(1 << 7)
#define FP_DETECT_SENSE			(1 << 8)
#define R200_FP_SOURCE_SEL_MASK		(3 << 10)
#define R200_FP_SOURCE_SEL_CRTC1	(0 << 10)
#define R200_FP_SOURCE_SEL_CRTC2	(1 << 10)
#define R200_FP_SOURCE_SEL_RMX		(2 << 10)
#define R200_FP_SOURCE_SEL_TRANS	(3 << 10)
#define FP_SEL_CRTC1			(0 << 13)
#define FP_SEL_CRTC2			(1 << 13)
#define FP_USE_VGA_HSYNC		(1 << 14)
#define FP_CRTC_DONT_SHADOW_HPAR	(1 << 15)
#define FP_CRTC_DONT_SHADOW_VPAR	(1 << 16)
#define FP_CRTC_DONT_SHADOW_HEND	(1 << 17)
#define FP_CRTC_USE_SHADOW_VEND		(1 << 18)
#define FP_RMX_HVSYNC_CONTROL_EN	(1 << 20)
#define FP_DFP_SYNC_SEL			(1 << 21)
#define FP_CRTC_LOCK_8DOT		(1 << 22)
#define FP_CRT_SYNC_SEL			(1 << 23)
#define FP_USE_SHADOW_EN		(1 << 24)
#define FP_CRT_SYNC_ALT			(1 << 26)

/* FP2_GEN_CNTL bit constants */
#define FP2_BLANK_EN			(1 <<	1)
#define FP2_ON				(1 <<	2)
#define FP2_PANEL_FORMAT		(1 <<	3)
#define FP2_SOURCE_SEL_MASK		(3 << 10)
#define FP2_SOURCE_SEL_CRTC2		(1 << 10)
#define FP2_SRC_SEL_MASK		(3 << 13)
#define FP2_SRC_SEL_CRTC2		(1 << 13)
#define FP2_FP_POL			(1 << 16)
#define FP2_LP_POL			(1 << 17)
#define FP2_SCK_POL			(1 << 18)
#define FP2_LCD_CNTL_MASK		(7 << 19)
#define FP2_PAD_FLOP_EN			(1 << 22)
#define FP2_CRC_EN			(1 << 23)
#define FP2_CRC_READ_EN			(1 << 24)
#define FP2_DV0_EN			(1 << 25)
#define FP2_DV0_RATE_SEL_SDR		(1 << 26)


/* LVDS_GEN_CNTL bit constants */
#define LVDS_ON				(1 << 0)
#define LVDS_DISPLAY_DIS		(1 << 1)
#define LVDS_PANEL_TYPE			(1 << 2)
#define LVDS_PANEL_FORMAT		(1 << 3)
#define LVDS_EN				(1 << 7)
#define LVDS_BL_MOD_LEVEL_MASK		0x0000ff00
#define LVDS_BL_MOD_LEVEL_SHIFT		8
#define LVDS_BL_MOD_EN			(1 << 16)
#define LVDS_DIGON			(1 << 18)
#define LVDS_BLON			(1 << 19)
#define LVDS_SEL_CRTC2			(1 << 23)
#define LVDS_STATE_MASK \
	(LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)

/* LVDS_PLL_CNTL bit constatns */
#define HSYNC_DELAY_SHIFT		0x1c
#define HSYNC_DELAY_MASK		(0xf << 0x1c)

/* TMDS_TRANSMITTER_CNTL bit constants */
#define TMDS_PLL_EN			(1 << 0)
#define TMDS_PLLRST			(1 << 1)
#define TMDS_RAN_PAT_RST		(1 << 7)