📄 mpc8323erdb.h
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/* * General PCI * Addresses are mapped 1-1. */#define CFG_PCI1_MEM_BASE 0x80000000#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */#define CFG_PCI1_MMIO_BASE 0x90000000#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */#define CFG_PCI1_IO_BASE 0xd0000000#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */#ifdef CONFIG_PCI#define CONFIG_NET_MULTI#define CONFIG_PCI_PNP /* do pci plug-and-play */#undef CONFIG_EEPRO100#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */#endif /* CONFIG_PCI */#ifndef CONFIG_NET_MULTI#define CONFIG_NET_MULTI 1#endif/* * QE UEC ethernet configuration */#define CONFIG_UEC_ETH#define CONFIG_ETHPRIME "Freescale GETH"#define CONFIG_UEC_ETH1 /* ETH3 */#ifdef CONFIG_UEC_ETH1#define CFG_UEC1_UCC_NUM 2 /* UCC3 */#define CFG_UEC1_RX_CLK QE_CLK9#define CFG_UEC1_TX_CLK QE_CLK10#define CFG_UEC1_ETH_TYPE FAST_ETH#define CFG_UEC1_PHY_ADDR 4#define CFG_UEC1_INTERFACE_MODE ENET_100_MII#endif#define CONFIG_UEC_ETH2 /* ETH4 */#ifdef CONFIG_UEC_ETH2#define CFG_UEC2_UCC_NUM 1 /* UCC2 */#define CFG_UEC2_RX_CLK QE_CLK16#define CFG_UEC2_TX_CLK QE_CLK3#define CFG_UEC2_ETH_TYPE FAST_ETH#define CFG_UEC2_PHY_ADDR 0#define CFG_UEC2_INTERFACE_MODE ENET_100_MII#endif/* * Environment */#ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000#else #define CFG_NO_FLASH 1 /* Flash is not usable now */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_SIZE 0x2000#endif#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change *//* * BOOTP options */#define CONFIG_BOOTP_BOOTFILESIZE#define CONFIG_BOOTP_BOOTPATH#define CONFIG_BOOTP_GATEWAY#define CONFIG_BOOTP_HOSTNAME/* * Command line configuration. */#include <config_cmd_default.h>#define CONFIG_CMD_PING#define CONFIG_CMD_I2C#define CONFIG_CMD_ASKENV#if defined(CONFIG_PCI) #define CONFIG_CMD_PCI#endif#if defined(CFG_RAMBOOT) #undef CONFIG_CMD_ENV #undef CONFIG_CMD_LOADS#endif#undef CONFIG_WATCHDOG /* watchdog disabled *//* * Miscellaneous configurable options */#define CFG_LONGHELP /* undef to save memory */#define CFG_LOAD_ADDR 0x2000000 /* default load address */#define CFG_PROMPT "=> " /* Monitor Command Prompt */#if (CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */#else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */#endif#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define CFG_MAXARGS 16 /* max number of command args */#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */#define CFG_HZ 1000 /* decrementer freq: 1ms ticks *//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux *//* * Core HID Setup */#define CFG_HID0_INIT 0x000000000#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK#define CFG_HID2 HID2_HBE/* * Cache Config */#define CFG_DCACHE_SIZE 16384#define CFG_CACHELINE_SIZE 32#if defined(CONFIG_CMD_KGDB)#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */#endif/* * MMU Setup *//* DDR: cache cacheable */#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT0L CFG_IBAT0L#define CFG_DBAT0U CFG_IBAT0U/* IMMRBAR & PCI IO: cache-inhibit and guarded */#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)#define CFG_DBAT1L CFG_IBAT1L#define CFG_DBAT1U CFG_IBAT1U/* FLASH: icache cacheable, but dcache-inhibit and guarded */#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_DBAT2U CFG_IBAT2U#define CFG_IBAT3L (0)#define CFG_IBAT3U (0)#define CFG_DBAT3L CFG_IBAT3L#define CFG_DBAT3U CFG_IBAT3U/* Stack in dcache: cacheable, no memory coherence */#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)#define CFG_DBAT4L CFG_IBAT4L#define CFG_DBAT4U CFG_IBAT4U#ifdef CONFIG_PCI/* PCI MEM space: cacheable */#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT5L CFG_IBAT5L#define CFG_DBAT5U CFG_IBAT5U/* PCI MMIO space: cache-inhibit and guarded */#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)#define CFG_DBAT6L CFG_IBAT6L#define CFG_DBAT6U CFG_IBAT6U#else#define CFG_IBAT5L (0)#define CFG_IBAT5U (0)#define CFG_IBAT6L (0)#define CFG_IBAT6U (0)#define CFG_DBAT5L CFG_IBAT5L#define CFG_DBAT5U CFG_IBAT5U#define CFG_DBAT6L CFG_IBAT6L#define CFG_DBAT6U CFG_IBAT6U#endif/* Nothing in BAT7 */#define CFG_IBAT7L (0)#define CFG_IBAT7U (0)#define CFG_DBAT7L CFG_IBAT7L#define CFG_DBAT7U CFG_IBAT7U/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */#define BOOTFLAG_WARM 0x02 /* Software reboot */#if (CONFIG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */#endif/* * Environment Configuration */#define CONFIG_ENV_OVERWRITE#define CONFIG_ETHADDR 00:04:9f:ef:03:01#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02#define CONFIG_IPADDR 10.0.0.2#define CONFIG_SERVERIP 10.0.0.1#define CONFIG_GATEWAYIP 10.0.0.1#define CONFIG_NETMASK 255.0.0.0#define CONFIG_NETDEV eth1#define CONFIG_HOSTNAME mpc8323erdb#define CONFIG_ROOTPATH /nfsroot#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot#define CONFIG_BOOTFILE uImage#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */#define CONFIG_FDTFILE mpc832x_rdb.dtb#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */#define CONFIG_BAUDRATE 115200#define XMK_STR(x) #x#define MK_STR(x) XMK_STR(x)#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ "erase " MK_STR(TEXT_BASE) " +$filesize; " \ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ "console=ttyS0\0" \ "setbootargs=setenv bootargs " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0"#define CONFIG_NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setbootargs;" \ "run setipargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr"#define CONFIG_RAMBOOTCOMMAND \ "setenv rootdev /dev/ram;" \ "run setbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr $ramdiskaddr $fdtaddr"#undef MK_STR#undef XMK_STR#endif /* __CONFIG_H */
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