tigon3.h

U-boot源码 ARM7启动代码

#define TX_STATUS_SENT_XON                          BIT_2
#define TX_STATUS_LINK_UP                           BIT_3
#define TX_STATUS_ODI_UNDERRUN                      BIT_4
#define TX_STATUS_ODI_OVERRUN                       BIT_5

	/* Transmit MAC length. */
	T3_32BIT_REGISTER TxLengths;
#define TX_LEN_SLOT_TIME_MASK                       0xff
#define TX_LEN_IPG_MASK                             0x0f00
#define TX_LEN_IPG_CRS_MASK                         (BIT_12 | BIT_13)

	/* Receive MAC mode. */
	T3_32BIT_REGISTER RxMode;
#define RX_MODE_RESET                               BIT_0
#define RX_MODE_ENABLE                              BIT_1
#define RX_MODE_ENABLE_FLOW_CONTROL                 BIT_2
#define RX_MODE_KEEP_MAC_CONTROL                    BIT_3
#define RX_MODE_KEEP_PAUSE                          BIT_4
#define RX_MODE_ACCEPT_OVERSIZED                    BIT_5
#define RX_MODE_ACCEPT_RUNTS                        BIT_6
#define RX_MODE_LENGTH_CHECK                        BIT_7
#define RX_MODE_PROMISCUOUS_MODE                    BIT_8
#define RX_MODE_NO_CRC_CHECK                        BIT_9
#define RX_MODE_KEEP_VLAN_TAG                       BIT_10

	/* Receive MAC status. */
	T3_32BIT_REGISTER RxStatus;
#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED         BIT_0
#define RX_STATUS_XOFF_RECEIVED                     BIT_1
#define RX_STATUS_XON_RECEIVED                      BIT_2

	/* Hash registers. */
	T3_32BIT_REGISTER HashReg[4];

	/* Receive placement rules registers. */
	struct {
		T3_32BIT_REGISTER Rule;
		T3_32BIT_REGISTER Value;
	} RcvRules[16];

#define RCV_DISABLE_RULE_MASK                       0x7fffffff

#define RCV_RULE1_REJECT_BROADCAST_IDX              0x00
#define REJECT_BROADCAST_RULE1_RULE                 0xc2000000
#define REJECT_BROADCAST_RULE1_VALUE                0xffffffff

#define RCV_RULE2_REJECT_BROADCAST_IDX              0x01
#define REJECT_BROADCAST_RULE2_RULE                 0x86000004
#define REJECT_BROADCAST_RULE2_VALUE                0xffffffff

#if INCLUDE_5701_AX_FIX
#define RCV_LAST_RULE_IDX                           0x04
#else
#define RCV_LAST_RULE_IDX                           0x02
#endif

	T3_32BIT_REGISTER RcvRuleCfg;
#define RX_RULE_DEFAULT_CLASS                       (1 << 3)

	LM_UINT8 Reserved1[140];

	T3_32BIT_REGISTER SerdesCfg;
	T3_32BIT_REGISTER SerdesStatus;

	LM_UINT8 Reserved2[104];

	volatile LM_UINT8 TxMacState[16];
	volatile LM_UINT8 RxMacState[20];

	LM_UINT8 Reserved3[476];

	T3_32BIT_REGISTER RxStats[26];

	LM_UINT8 Reserved4[24];

	T3_32BIT_REGISTER TxStats[28];

	LM_UINT8 Reserved5[784];
} T3_MAC_CONTROL, *PT3_MAC_CONTROL;

/******************************************************************************/
/* Send data initiator control registers. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define T3_SND_DATA_IN_MODE_RESET                       BIT_0
#define T3_SND_DATA_IN_MODE_ENABLE                      BIT_1
#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE      BIT_2

	T3_32BIT_REGISTER Status;
#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN           BIT_2

	T3_32BIT_REGISTER StatsCtrl;
#define T3_SND_DATA_IN_STATS_CTRL_ENABLE                BIT_0
#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE         BIT_1
#define T3_SND_DATA_IN_STATS_CTRL_CLEAR                 BIT_2
#define T3_SND_DATA_IN_STATS_CTRL_FLUSH                 BIT_3
#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO            BIT_4

	T3_32BIT_REGISTER StatsEnableMask;
	T3_32BIT_REGISTER StatsIncMask;

	LM_UINT8 Reserved[108];

	T3_32BIT_REGISTER ClassOfServCnt[16];
	T3_32BIT_REGISTER DmaReadQFullCnt;
	T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
	T3_32BIT_REGISTER SdcQFullCnt;

	T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
	T3_32BIT_REGISTER StatusUpdatedCnt;
	T3_32BIT_REGISTER InterruptsCnt;
	T3_32BIT_REGISTER AvoidInterruptsCnt;
	T3_32BIT_REGISTER SendThresholdHitCnt;

	/* Unused space. */
	LM_UINT8 Unused[800];
} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;

/******************************************************************************/
/* Send data completion control registers. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define SND_DATA_COMP_MODE_RESET                        BIT_0
#define SND_DATA_COMP_MODE_ENABLE                       BIT_1

	/* Unused space. */
	LM_UINT8 Unused[1020];
} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;

/******************************************************************************/
/* Send BD Ring Selector Control Registers. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define SND_BD_SEL_MODE_RESET                           BIT_0
#define SND_BD_SEL_MODE_ENABLE                          BIT_1
#define SND_BD_SEL_MODE_ATTN_ENABLE                     BIT_2

	T3_32BIT_REGISTER Status;
#define SND_BD_SEL_STATUS_ERROR_ATTN                    BIT_2

	T3_32BIT_REGISTER HwDiag;

	/* Unused space. */
	LM_UINT8 Unused1[52];

	/* Send BD Ring Selector Local NIC Send BD Consumer Index. */
	T3_32BIT_REGISTER NicSendBdSelConIdx[16];

	/* Unused space. */
	LM_UINT8 Unused2[896];
} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;

/******************************************************************************/
/* Send BD initiator control registers. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define SND_BD_IN_MODE_RESET                            BIT_0
#define SND_BD_IN_MODE_ENABLE                           BIT_1
#define SND_BD_IN_MODE_ATTN_ENABLE                      BIT_2

	T3_32BIT_REGISTER Status;
#define SND_BD_IN_STATUS_ERROR_ATTN                     BIT_2

	/* Send BD initiator local NIC send BD producer index. */
	T3_32BIT_REGISTER NicSendBdInProdIdx[16];

	/* Unused space. */
	LM_UINT8 Unused2[952];
} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;

/******************************************************************************/
/* Send BD Completion Control. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define SND_BD_COMP_MODE_RESET                          BIT_0
#define SND_BD_COMP_MODE_ENABLE                         BIT_1
#define SND_BD_COMP_MODE_ATTN_ENABLE                    BIT_2

	/* Unused space. */
	LM_UINT8 Unused2[1020];
} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;

/******************************************************************************/
/* Receive list placement control registers. */
/******************************************************************************/

typedef struct {
	/* Mode. */
	T3_32BIT_REGISTER Mode;
#define RCV_LIST_PLMT_MODE_RESET                        BIT_0
#define RCV_LIST_PLMT_MODE_ENABLE                       BIT_1
#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE           BIT_2
#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE      BIT_3
#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE      BIT_4

	/* Status. */
	T3_32BIT_REGISTER Status;
#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN                BIT_2
#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN               BIT_3
#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN           BIT_4

	/* Receive selector list lock register. */
	T3_32BIT_REGISTER Lock;
#define RCV_LIST_SEL_LOCK_REQUEST_MASK                  0xffff
#define RCV_LIST_SEL_LOCK_GRANT_MASK                    0xffff0000

	/* Selector non-empty bits. */
	T3_32BIT_REGISTER NonEmptyBits;
#define RCV_LIST_SEL_NON_EMPTY_MASK                     0xffff

	/* Receive list placement configuration register. */
	T3_32BIT_REGISTER Config;

	/* Receive List Placement statistics Control. */
	T3_32BIT_REGISTER StatsCtrl;
#define RCV_LIST_STATS_ENABLE                               BIT_0
#define RCV_LIST_STATS_FAST_UPDATE                          BIT_1

	/* Receive List Placement statistics Enable Mask. */
	T3_32BIT_REGISTER StatsEnableMask;

	/* Receive List Placement statistics Increment Mask. */
	T3_32BIT_REGISTER StatsIncMask;

	/* Unused space. */
	LM_UINT8 Unused1[224];

	struct {
		T3_32BIT_REGISTER Head;
		T3_32BIT_REGISTER Tail;
		T3_32BIT_REGISTER Count;

		/* Unused space. */
		LM_UINT8 Unused[4];
	} RcvSelectorList[16];

	/* Local statistics counter. */
	T3_32BIT_REGISTER ClassOfServCnt[16];

	T3_32BIT_REGISTER DropDueToFilterCnt;
	T3_32BIT_REGISTER DmaWriteQFullCnt;
	T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
	T3_32BIT_REGISTER NoMoreReceiveBdCnt;
	T3_32BIT_REGISTER IfInDiscardsCnt;
	T3_32BIT_REGISTER IfInErrorsCnt;
	T3_32BIT_REGISTER RcvThresholdHitCnt;

	/* Another unused space. */
	LM_UINT8 Unused2[420];
} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;

/******************************************************************************/
/* Receive Data and Receive BD Initiator Control. */
/******************************************************************************/

typedef struct {
	/* Mode. */
	T3_32BIT_REGISTER Mode;
#define RCV_DATA_BD_IN_MODE_RESET                   BIT_0
#define RCV_DATA_BD_IN_MODE_ENABLE                  BIT_1
#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED         BIT_2
#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG           BIT_3
#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE       BIT_4

	/* Status. */
	T3_32BIT_REGISTER Status;
#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED       BIT_2
#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG         BIT_3
#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE     BIT_4

	/* Split frame minium size. */
	T3_32BIT_REGISTER SplitFrameMinSize;

	/* Unused space. */
	LM_UINT8 Unused1[0x2440 - 0x240c];

	/* Receive RCBs. */
	T3_RCB JumboRcvRcb;
	T3_RCB StdRcvRcb;
	T3_RCB MiniRcvRcb;

	/* Receive Data and Receive BD Ring Initiator Local NIC Receive */
	/* BD Consumber Index. */
	T3_32BIT_REGISTER NicJumboConIdx;
	T3_32BIT_REGISTER NicStdConIdx;
	T3_32BIT_REGISTER NicMiniConIdx;

	/* Unused space. */
	LM_UINT8 Unused2[4];

	/* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
	T3_32BIT_REGISTER RcvDataBdProdIdx[16];

	/* Receive Data and Receive BD Initiator Hardware Diagnostic. */
	T3_32BIT_REGISTER HwDiag;

	/* Unused space. */
	LM_UINT8 Unused3[828];
} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;

/******************************************************************************/
/* Receive Data Completion Control Registes. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define RCV_DATA_COMP_MODE_RESET                        BIT_0
#define RCV_DATA_COMP_MODE_ENABLE                       BIT_1
#define RCV_DATA_COMP_MODE_ATTN_ENABLE                  BIT_2

	/* Unused spaced. */
	LM_UINT8 Unused[1020];
} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;

/******************************************************************************/
/* Receive BD Initiator Control. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define RCV_BD_IN_MODE_RESET                            BIT_0
#define RCV_BD_IN_MODE_ENABLE                           BIT_1
#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE    BIT_2

	T3_32BIT_REGISTER Status;
#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN         BIT_2

	T3_32BIT_REGISTER NicJumboRcvProdIdx;
	T3_32BIT_REGISTER NicStdRcvProdIdx;
	T3_32BIT_REGISTER NicMiniRcvProdIdx;

	T3_32BIT_REGISTER MiniRcvThreshold;
	T3_32BIT_REGISTER StdRcvThreshold;
	T3_32BIT_REGISTER JumboRcvThreshold;

	/* Unused space. */
	LM_UINT8 Unused[992];
} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;

/******************************************************************************/
/* Receive BD Completion Control Registers. */
/******************************************************************************/

typedef struct {
	T3_32BIT_REGISTER Mode;
#define RCV_BD_COMP_MODE_RESET                          BIT_0
#define RCV_BD_COMP_MODE_ENABLE                         BIT_1
#define RCV_BD_COMP_MODE_ATTN_ENABLE                    BIT_2

	T3_32BIT_REGISTER Status;
#define RCV_BD_COMP_STATUS_ERROR_ATTN                   BIT_2

	T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
	T3_32BIT_REGISTER NicStdRcvBdProdIdx;
	T3_32BIT_REGISTER NicMiniRcvBdProdIdx;

	/* Unused space. */
	LM_UINT8 Unused[1004];
} T3_RCV_BD_COMPLETION,