tigon3.h

U-boot源码 ARM7启动代码

	T3_64BIT_REGISTER Reserved3;
	T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
	T3_64BIT_REGISTER dot3StatsLateCollisions;
	T3_64BIT_REGISTER dot3Collided2Times;
	T3_64BIT_REGISTER dot3Collided3Times;
	T3_64BIT_REGISTER dot3Collided4Times;
	T3_64BIT_REGISTER dot3Collided5Times;
	T3_64BIT_REGISTER dot3Collided6Times;
	T3_64BIT_REGISTER dot3Collided7Times;
	T3_64BIT_REGISTER dot3Collided8Times;
	T3_64BIT_REGISTER dot3Collided9Times;
	T3_64BIT_REGISTER dot3Collided10Times;
	T3_64BIT_REGISTER dot3Collided11Times;
	T3_64BIT_REGISTER dot3Collided12Times;
	T3_64BIT_REGISTER dot3Collided13Times;
	T3_64BIT_REGISTER dot3Collided14Times;
	T3_64BIT_REGISTER dot3Collided15Times;
	T3_64BIT_REGISTER ifHCOutUcastPkts;
	T3_64BIT_REGISTER ifHCOutMulticastPkts;
	T3_64BIT_REGISTER ifHCOutBroadcastPkts;
	T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
	T3_64BIT_REGISTER ifOutDiscards;
	T3_64BIT_REGISTER ifOutErrors;

	T3_64BIT_REGISTER Unused2[31];

	/* Statistics maintained by Receive List Placement. */
	T3_64BIT_REGISTER COSIfHCInPkts[16];
	T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
	T3_64BIT_REGISTER nicDmaWriteQueueFull;
	T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
	T3_64BIT_REGISTER nicNoMoreRxBDs;
	T3_64BIT_REGISTER ifInDiscards;
	T3_64BIT_REGISTER ifInErrors;
	T3_64BIT_REGISTER nicRecvThresholdHit;

	T3_64BIT_REGISTER Unused3[9];

	/* Statistics maintained by Send Data Initiator. */
	T3_64BIT_REGISTER COSIfHCOutPkts[16];
	T3_64BIT_REGISTER nicDmaReadQueueFull;
	T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
	T3_64BIT_REGISTER nicSendDataCompQueueFull;

	/* Statistics maintained by Host Coalescing. */
	T3_64BIT_REGISTER nicRingSetSendProdIndex;
	T3_64BIT_REGISTER nicRingStatusUpdate;
	T3_64BIT_REGISTER nicInterrupts;
	T3_64BIT_REGISTER nicAvoidedInterrupts;
	T3_64BIT_REGISTER nicSendThresholdHit;

	LM_UINT8 Reserved4[0xb00 - 0x9c0];
} T3_STATS_BLOCK, *PT3_STATS_BLOCK;

/******************************************************************************/
/* PCI configuration registers. */
/******************************************************************************/

typedef struct {
	T3_16BIT_REGISTER VendorId;
	T3_16BIT_REGISTER DeviceId;

	T3_16BIT_REGISTER Command;
	T3_16BIT_REGISTER Status;

	T3_32BIT_REGISTER ClassCodeRevId;

	T3_8BIT_REGISTER CacheLineSize;
	T3_8BIT_REGISTER LatencyTimer;
	T3_8BIT_REGISTER HeaderType;
	T3_8BIT_REGISTER Bist;

	T3_32BIT_REGISTER MemBaseAddrLow;
	T3_32BIT_REGISTER MemBaseAddrHigh;

	LM_UINT8 Unused1[20];

	T3_16BIT_REGISTER SubsystemVendorId;
	T3_16BIT_REGISTER SubsystemId;

	T3_32BIT_REGISTER RomBaseAddr;

	T3_8BIT_REGISTER PciXCapiblityPtr;
	LM_UINT8 Unused2[7];

	T3_8BIT_REGISTER IntLine;
	T3_8BIT_REGISTER IntPin;
	T3_8BIT_REGISTER MinGnt;
	T3_8BIT_REGISTER MaxLat;

	T3_8BIT_REGISTER PciXCapabilities;
	T3_8BIT_REGISTER PmCapabilityPtr;
	T3_16BIT_REGISTER PciXCommand;

	T3_32BIT_REGISTER PciXStatus;

	T3_8BIT_REGISTER PmCapabilityId;
	T3_8BIT_REGISTER VpdCapabilityPtr;
	T3_16BIT_REGISTER PmCapabilities;

	T3_16BIT_REGISTER PmCtrlStatus;
#define PM_CTRL_PME_STATUS            BIT_15
#define PM_CTRL_PME_ENABLE            BIT_8
#define PM_CTRL_PME_POWER_STATE_D0    0
#define PM_CTRL_PME_POWER_STATE_D1    1
#define PM_CTRL_PME_POWER_STATE_D2    2
#define PM_CTRL_PME_POWER_STATE_D3H   3

	T3_8BIT_REGISTER BridgeSupportExt;
	T3_8BIT_REGISTER PmData;

	T3_8BIT_REGISTER VpdCapabilityId;
	T3_8BIT_REGISTER MsiCapabilityPtr;
	T3_16BIT_REGISTER VpdAddrFlag;
#define VPD_FLAG_WRITE      (1 << 15)
#define VPD_FLAG_RW_MASK    (1 << 15)
#define VPD_FLAG_READ       0

	T3_32BIT_REGISTER VpdData;

	T3_8BIT_REGISTER MsiCapabilityId;
	T3_8BIT_REGISTER NextCapabilityPtr;
	T3_16BIT_REGISTER MsiCtrl;
#define MSI_CTRL_64BIT_CAP     (1 << 7)
#define MSI_CTRL_MSG_ENABLE(x) (x << 4)
#define MSI_CTRL_MSG_CAP(x)    (x << 1)
#define MSI_CTRL_ENABLE        (1 << 0)

	T3_32BIT_REGISTER MsiAddrLow;
	T3_32BIT_REGISTER MsiAddrHigh;

	T3_16BIT_REGISTER MsiData;
	T3_16BIT_REGISTER Unused3;

	T3_32BIT_REGISTER MiscHostCtrl;
#define MISC_HOST_CTRL_CLEAR_INT                        BIT_0
#define MISC_HOST_CTRL_MASK_PCI_INT                     BIT_1
#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP          BIT_2
#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP          BIT_3
#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW          BIT_4
#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW                BIT_5
#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP             BIT_6
#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS           BIT_7
#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE             BIT_8
#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE        BIT_9

	T3_32BIT_REGISTER DmaReadWriteCtrl;
#define DMA_CTRL_WRITE_BOUNDARY_MASK            (BIT_11 | BIT_12 | BIT_13)
#define DMA_CTRL_WRITE_BOUNDARY_DISABLE         0
#define DMA_CTRL_WRITE_BOUNDARY_16              BIT_11
#define DMA_CTRL_WRITE_BOUNDARY_32              BIT_12
#define DMA_CTRL_WRITE_BOUNDARY_64              (BIT_12 | BIT_11)
#define DMA_CTRL_WRITE_BOUNDARY_128             BIT_13
#define DMA_CTRL_WRITE_BOUNDARY_256             (BIT_13 | BIT_11)
#define DMA_CTRL_WRITE_BOUNDARY_512             (BIT_13 | BIT_12)
#define DMA_CTRL_WRITE_BOUNDARY_1024            (BIT_13 | BIT_12 | BIT_11)
#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE          BIT_14

	T3_32BIT_REGISTER PciState;
#define T3_PCI_STATE_FORCE_PCI_RESET                    BIT_0
#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE               BIT_1
#define T3_PCI_STATE_NOT_PCI_X_BUS                      BIT_2
#define T3_PCI_STATE_HIGH_BUS_SPEED                     BIT_3
#define T3_PCI_STATE_32BIT_PCI_BUS                      BIT_4
#define T3_PCI_STATE_PCI_ROM_ENABLE                     BIT_5
#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE               BIT_6
#define T3_PCI_STATE_FLAT_VIEW                          BIT_8
#define T3_PCI_STATE_RETRY_SAME_DMA                     BIT_13

	T3_32BIT_REGISTER ClockCtrl;
#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE                BIT_11
#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE                BIT_10
#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE                 BIT_9

	T3_32BIT_REGISTER RegBaseAddr;

	T3_32BIT_REGISTER MemWindowBaseAddr;

#ifdef NIC_CPU_VIEW
	/* These registers are ONLY visible to NIC CPU */
	T3_32BIT_REGISTER PowerConsumed;
	T3_32BIT_REGISTER PowerDissipated;
#else				/* NIC_CPU_VIEW */
	T3_32BIT_REGISTER RegData;
	T3_32BIT_REGISTER MemWindowData;
#endif				/* !NIC_CPU_VIEW */

	T3_32BIT_REGISTER ModeCtrl;

	T3_32BIT_REGISTER MiscCfg;

	T3_32BIT_REGISTER MiscLocalCtrl;

	T3_32BIT_REGISTER Unused4;

	/* NOTE: Big/Little-endian clarification needed.  Are these register */
	/* in big or little endian formate. */
	T3_64BIT_REGISTER StdRingProdIdx;
	T3_64BIT_REGISTER RcvRetRingConIdx;
	T3_64BIT_REGISTER SndProdIdx;

	LM_UINT8 Unused5[80];
} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;

#define PCIX_CMD_MAX_SPLIT_MASK                         0x0070
#define PCIX_CMD_MAX_SPLIT_SHL                          4
#define PCIX_CMD_MAX_BURST_MASK                         0x000c
#define PCIX_CMD_MAX_BURST_SHL                          2
#define PCIX_CMD_MAX_BURST_CPIOB                        2

/******************************************************************************/
/* Mac control registers. */
/******************************************************************************/

typedef struct {
	/* MAC mode control. */
	T3_32BIT_REGISTER Mode;
#define MAC_MODE_GLOBAL_RESET                       BIT_0
#define MAC_MODE_HALF_DUPLEX                        BIT_1
#define MAC_MODE_PORT_MODE_MASK                     (BIT_2 | BIT_3)
#define MAC_MODE_PORT_MODE_TBI                      (BIT_2 | BIT_3)
#define MAC_MODE_PORT_MODE_GMII                     BIT_3
#define MAC_MODE_PORT_MODE_MII                      BIT_2
#define MAC_MODE_PORT_MODE_NONE                     BIT_NONE
#define MAC_MODE_PORT_INTERNAL_LOOPBACK             BIT_4
#define MAC_MODE_TAGGED_MAC_CONTROL                 BIT_7
#define MAC_MODE_TX_BURSTING                        BIT_8
#define MAC_MODE_MAX_DEFER                          BIT_9
#define MAC_MODE_LINK_POLARITY                      BIT_10
#define MAC_MODE_ENABLE_RX_STATISTICS               BIT_11
#define MAC_MODE_CLEAR_RX_STATISTICS                BIT_12
#define MAC_MODE_FLUSH_RX_STATISTICS                BIT_13
#define MAC_MODE_ENABLE_TX_STATISTICS               BIT_14
#define MAC_MODE_CLEAR_TX_STATISTICS                BIT_15
#define MAC_MODE_FLUSH_TX_STATISTICS                BIT_16
#define MAC_MODE_SEND_CONFIGS                       BIT_17
#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE         BIT_18
#define MAC_MODE_ACPI_POWER_ON_ENABLE               BIT_19
#define MAC_MODE_ENABLE_MIP                         BIT_20
#define MAC_MODE_ENABLE_TDE                         BIT_21
#define MAC_MODE_ENABLE_RDE                         BIT_22
#define MAC_MODE_ENABLE_FHDE                        BIT_23

	/* MAC status */
	T3_32BIT_REGISTER Status;
#define MAC_STATUS_PCS_SYNCED                       BIT_0
#define MAC_STATUS_SIGNAL_DETECTED                  BIT_1
#define MAC_STATUS_RECEIVING_CFG                    BIT_2
#define MAC_STATUS_CFG_CHANGED                      BIT_3
#define MAC_STATUS_SYNC_CHANGED                     BIT_4
#define MAC_STATUS_PORT_DECODE_ERROR                BIT_10
#define MAC_STATUS_LINK_STATE_CHANGED               BIT_12
#define MAC_STATUS_MI_COMPLETION                    BIT_22
#define MAC_STATUS_MI_INTERRUPT                     BIT_23
#define MAC_STATUS_AP_ERROR                         BIT_24
#define MAC_STATUS_ODI_ERROR                        BIT_25
#define MAC_STATUS_RX_STATS_OVERRUN                 BIT_26
#define MAC_STATUS_TX_STATS_OVERRUN                 BIT_27

	/* Event Enable */
	T3_32BIT_REGISTER MacEvent;
#define MAC_EVENT_ENABLE_PORT_DECODE_ERR            BIT_10
#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN    BIT_12
#define MAC_EVENT_ENABLE_MI_COMPLETION              BIT_22
#define MAC_EVENT_ENABLE_MI_INTERRUPT               BIT_23
#define MAC_EVENT_ENABLE_AP_ERROR                   BIT_24
#define MAC_EVENT_ENABLE_ODI_ERROR                  BIT_25
#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN           BIT_26
#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN           BIT_27

	/* Led control. */
	T3_32BIT_REGISTER LedCtrl;
#define LED_CTRL_OVERRIDE_LINK_LED                  BIT_0
#define LED_CTRL_1000MBPS_LED_ON                    BIT_1
#define LED_CTRL_100MBPS_LED_ON                     BIT_2
#define LED_CTRL_10MBPS_LED_ON                      BIT_3
#define LED_CTRL_OVERRIDE_TRAFFIC_LED               BIT_4
#define LED_CTRL_BLINK_TRAFFIC_LED                  BIT_5
#define LED_CTRL_TRAFFIC_LED                        BIT_6
#define LED_CTRL_1000MBPS_LED_STATUS                BIT_7
#define LED_CTRL_100MBPS_LED_STATUS                 BIT_8
#define LED_CTRL_10MBPS_LED_STATUS                  BIT_9
#define LED_CTRL_TRAFFIC_LED_STATUS                 BIT_10
#define LED_CTRL_MAC_MODE                           BIT_NONE
#define LED_CTRL_PHY_MODE_1                         BIT_11
#define LED_CTRL_PHY_MODE_2                         BIT_12
#define LED_CTRL_BLINK_RATE_MASK                    0x7ff80000
#define LED_CTRL_OVERRIDE_BLINK_PERIOD              BIT_19
#define LED_CTRL_OVERRIDE_BLINK_RATE                BIT_31

	/* MAC addresses. */
	struct {
		T3_32BIT_REGISTER High;	/* Upper 2 bytes. */
		T3_32BIT_REGISTER Low;	/* Lower 4 bytes. */
	} MacAddr[4];

	/* ACPI Mbuf pointer. */
	T3_32BIT_REGISTER AcpiMbufPtr;

	/* ACPI Length and Offset. */
	T3_32BIT_REGISTER AcpiLengthOffset;
#define ACPI_LENGTH_MASK                            0xffff
#define ACPI_OFFSET_MASK                            0x0fff0000
#define ACPI_LENGTH(x)                              x
#define ACPI_OFFSET(x)                              ((x) << 16)

	/* Transmit random backoff. */
	T3_32BIT_REGISTER TxBackoffSeed;
#define MAC_TX_BACKOFF_SEED_MASK                    0x3ff

	/* Receive MTU */
	T3_32BIT_REGISTER MtuSize;
#define MAC_RX_MTU_MASK                             0xffff

	/* Gigabit PCS Test. */
	T3_32BIT_REGISTER PcsTest;
#define MAC_PCS_TEST_DATA_PATTERN_MASK              0x0fffff
#define MAC_PCS_TEST_ENABLE                         BIT_20

	/* Transmit Gigabit Auto-Negotiation. */
	T3_32BIT_REGISTER TxAutoNeg;
#define MAC_AN_TX_AN_DATA_MASK                      0xffff

	/* Receive Gigabit Auto-Negotiation. */
	T3_32BIT_REGISTER RxAutoNeg;
#define MAC_AN_RX_AN_DATA_MASK                      0xffff

	/* MI Communication. */
	T3_32BIT_REGISTER MiCom;
#define MI_COM_CMD_MASK                             (BIT_26 | BIT_27)
#define MI_COM_CMD_WRITE                            BIT_26
#define MI_COM_CMD_READ                             BIT_27
#define MI_COM_READ_FAILED                          BIT_28
#define MI_COM_START                                BIT_29
#define MI_COM_BUSY                                 BIT_29

#define MI_COM_PHY_ADDR_MASK                        0x1f
#define MI_COM_FIRST_PHY_ADDR_BIT                   21

#define MI_COM_PHY_REG_ADDR_MASK                    0x1f
#define MI_COM_FIRST_PHY_REG_ADDR_BIT               16

#define MI_COM_PHY_DATA_MASK                        0xffff

	/* MI Status. */
	T3_32BIT_REGISTER MiStatus;
#define MI_STATUS_ENABLE_LINK_STATUS_ATTN           BIT_0

	/* MI Mode. */
	T3_32BIT_REGISTER MiMode;
#define MI_MODE_CLOCK_SPEED_10MHZ                   BIT_0
#define MI_MODE_USE_SHORT_PREAMBLE                  BIT_1
#define MI_MODE_AUTO_POLLING_ENABLE                 BIT_4
#define MI_MODE_CORE_CLOCK_SPEED_62MHZ              BIT_15

	/* Auto-polling status. */
	T3_32BIT_REGISTER AutoPollStatus;
#define AUTO_POLL_ERROR                             BIT_0

	/* Transmit MAC mode. */
	T3_32BIT_REGISTER TxMode;
#define TX_MODE_RESET                               BIT_0
#define TX_MODE_ENABLE                              BIT_1
#define TX_MODE_ENABLE_FLOW_CONTROL                 BIT_4
#define TX_MODE_ENABLE_BIG_BACKOFF                  BIT_5
#define TX_MODE_ENABLE_LONG_PAUSE                   BIT_6

	/* Transmit MAC status. */
	T3_32BIT_REGISTER TxStatus;
#define TX_STATUS_RX_CURRENTLY_XOFFED               BIT_0
#define TX_STATUS_SENT_XOFF                         BIT_1