mult_add_ovq2.tdf

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR3" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="NO" DEVICE_FAMILY="Cyclone" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR3" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_ACLR_A="ACLR3" SIGNED_PIPELINE_ACLR_B="ACLR3" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=32 WIDTH_B=4 WIDTH_RESULT=32 aclr3 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 4.2 cbx_alt_ded_mult_y 2004:11:08:17:49:54:SJ cbx_altmult_add 2004:10:20:18:55:32:SJ cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_mgl 2004:10:26:10:32:18:SJ cbx_padd 2004:10:28:17:00:18:SJ cbx_parallel_add 2003:11:11:15:26:08:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ cbx_util_mgl 2004:09:29:16:04:00:SJ  VERSION_END


--  Copyright (C) 1988-2002 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
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--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
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--  limited to  modification,  reverse engineering,  de-compiling, or use  with
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include "alt_mac_mult.inc";
include "alt_mac_out.inc";

--synthesis_resources = alt_mac_mult 1 alt_mac_out 1 
SUBDESIGN mult_add_ovq2
( 
	aclr3	:	input;
	clock0	:	input;
	dataa[31..0]	:	input;
	datab[3..0]	:	input;
	result[31..0]	:	output;
) 
VARIABLE 
	mac_mult1 : alt_mac_mult
		WITH (
			DATAA_WIDTH = 32,
			DATAB_WIDTH = 4,
			OUTPUT_CLEAR = "A_3",
			OUTPUT_CLOCK = "A_0",
			OUTPUT_WIDTH = 36
		);
	mac_out2 : alt_mac_out
		WITH (
			DATAA_WIDTH = 36,
			OPERATION_MODE = "OUTPUT_ONLY",
			OUTPUT_WIDTH = 36
		);
	aclr0	: NODE;
	aclr1	: NODE;
	aclr2	: NODE;
	clock1	: NODE;
	clock2	: NODE;
	clock3	: NODE;
	dataa_bus[31..0]	: WIRE;
	datab_bus[3..0]	: WIRE;
	ena0	: NODE;
	ena1	: NODE;
	ena2	: NODE;
	ena3	: NODE;

BEGIN 
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0);
	mac_mult1.dataa[] = ( dataa_bus[31..0]);
	mac_mult1.datab[] = ( datab_bus[3..0]);
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_out2.aclr[] = ( aclr3, aclr2, aclr1, aclr0);
	mac_out2.clk[] = ( clock3, clock2, clock1, clock0);
	mac_out2.dataa[] = ( mac_mult1.dataout[35..0]);
	mac_out2.ena[] = ( ena3, ena2, ena1, ena0);
	mac_out2.signa = B"0";
	mac_out2.signb = B"0";
	aclr0 = GND;
	aclr1 = GND;
	aclr2 = GND;
	clock1 = VCC;
	clock2 = VCC;
	clock3 = VCC;
	dataa_bus[] = ( dataa[31..0]);
	datab_bus[] = ( datab[3..0]);
	ena0 = VCC;
	ena1 = VCC;
	ena2 = VCC;
	ena3 = VCC;
	result[31..0] = mac_out2.dataout[31..0];
END;
--VALID FILE