full_featured.map.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 high_res_timer.v(209) " "Warning: Verilog HDL assignment warning at high_res_timer.v(209): truncated value with size 4 to match size of target (1)" {  } { { "high_res_timer.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/high_res_timer.v" 209 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(3598) " "Warning: Verilog HDL assignment warning at full_1c20.v(3598): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3598 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 1 full_1c20.v(3677) " "Warning: Verilog HDL assignment warning at full_1c20.v(3677): truncated value with size 24 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3677 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "jtag_uart.v 7 7 " "Info: Using design file jtag_uart.v, which is not specified as a design file for the current project, but contains definitions for 7 design units and 7 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 jtag_uart_log_module " "Info: Found entity 1: jtag_uart_log_module" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 jtag_uart_sim_scfifo_w " "Info: Found entity 2: jtag_uart_sim_scfifo_w" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 65 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 jtag_uart_scfifo_w " "Info: Found entity 3: jtag_uart_scfifo_w" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 114 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 jtag_uart_drom_module " "Info: Found entity 4: jtag_uart_drom_module" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 188 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_sim_scfifo_r " "Info: Found entity 5: jtag_uart_sim_scfifo_r" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 332 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_scfifo_r " "Info: Found entity 6: jtag_uart_scfifo_r" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 411 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 jtag_uart " "Info: Found entity 7: jtag_uart" {  } { { "jtag_uart.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/jtag_uart.v" 487 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "e:/altera/libraries/megafunctions/scfifo.tdf" 240 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_1to.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_1to.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_1to " "Info: Found entity 1: scfifo_1to" {  } { { "db/scfifo_1to.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/scfifo_1to.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_83p.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_83p.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_83p " "Info: Found entity 1: a_dpfifo_83p" {  } { { "db/a_dpfifo_83p.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/a_dpfifo_83p.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Info: Found entity 1: a_fefifo_7cf" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/a_fefifo_7cf.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_9c7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_9c7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_9c7 " "Info: Found entity 1: cntr_9c7" {  } { { "db/cntr_9c7.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/cntr_9c7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_1cm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_1cm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_1cm " "Info: Found entity 1: dpram_1cm" {  } { { "db/dpram_1cm.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/dpram_1cm.tdf" 30 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_chc1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_chc1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_chc1 " "Info: Found entity 1: altsyncram_chc1" {  } { { "db/altsyncram_chc1.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_chc1.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rd8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rd8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rd8 " "Info: Found entity 1: cntr_rd8" {  } { { "db/cntr_rd8.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/cntr_rd8.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/alt_jtag_atlantic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/alt_jtag_atlantic.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_jtag_atlantic " "Info: Found entity 1: alt_jtag_atlantic" {  } { { "alt_jtag_atlantic.v" "" { Text "e:/altera/libraries/megafunctions/alt_jtag_atlantic.v" 104 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(3810) " "Warning: Verilog HDL assignment warning at full_1c20.v(3810): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3810 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 2 full_1c20.v(3883) " "Warning: Verilog HDL assignment warning at full_1c20.v(3883): truncated value with size 24 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3883 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "key_pio.v 1 1 " "Info: Using design file key_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 key_pio " "Info: Found entity 1: key_pio" {  } { { "key_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/key_pio.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 key_pio.v(79) " "Warning: Verilog HDL assignment warning at key_pio.v(79): truncated value with size 2 to match size of target (1)" {  } { { "key_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/key_pio.v" 79 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 key_pio.v(91) " "Warning: Verilog HDL assignment warning at key_pio.v(91): truncated value with size 2 to match size of target (1)" {  } { { "key_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/key_pio.v" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 key_pio.v(103) " "Warning: Verilog HDL assignment warning at key_pio.v(103): truncated value with size 2 to match size of target (1)" {  } { { "key_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/key_pio.v" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 key_pio.v(115) " "Warning: Verilog HDL assignment warning at key_pio.v(115): truncated value with size 2 to match size of target (1)" {  } { { "key_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/key_pio.v" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(4012) " "Warning: Verilog HDL assignment warning at full_1c20.v(4012): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4012 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 full_1c20.v(4054) " "Warning: Verilog HDL assignment warning at full_1c20.v(4054): truncated value with size 32 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4054 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 2 full_1c20.v(4088) " "Warning: Verilog HDL assignment warning at full_1c20.v(4088): truncated value with size 24 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4088 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lcd_ctrl.v 1 1 " "Info: Using design file lcd_ctrl.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_ctrl " "Info: Found entity 1: lcd_ctrl" {  } { { "lcd_ctrl.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/lcd_ctrl.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(42