full_featured.map.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2631) " "Warning: Verilog HDL assignment warning at full_1c20.v(2631): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2631 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 3 full_1c20.v(2643) " "Warning: Verilog HDL assignment warning at full_1c20.v(2643): truncated value with size 4 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2643 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(2650) " "Warning: Verilog HDL assignment warning at full_1c20.v(2650): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2650 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2700) " "Warning: Verilog HDL assignment warning at full_1c20.v(2700): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2700 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(2719) " "Warning: Verilog HDL assignment warning at full_1c20.v(2719): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2719 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2748) " "Warning: Verilog HDL assignment warning at full_1c20.v(2748): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2748 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2787) " "Warning: Verilog HDL assignment warning at full_1c20.v(2787): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2787 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2797) " "Warning: Verilog HDL assignment warning at full_1c20.v(2797): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2797 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2822) " "Warning: Verilog HDL assignment warning at full_1c20.v(2822): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2822 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(2831) " "Warning: Verilog HDL assignment warning at full_1c20.v(2831): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2831 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2856) " "Warning: Verilog HDL assignment warning at full_1c20.v(2856): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2856 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(2869) " "Warning: Verilog HDL assignment warning at full_1c20.v(2869): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2869 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2891) " "Warning: Verilog HDL assignment warning at full_1c20.v(2891): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2891 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(2900) " "Warning: Verilog HDL assignment warning at full_1c20.v(2900): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2900 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 full_1c20.v(2977) " "Warning: Verilog HDL assignment warning at full_1c20.v(2977): truncated value with size 5 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2977 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(3003) " "Warning: Verilog HDL assignment warning at full_1c20.v(3003): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3003 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(3013) " "Warning: Verilog HDL assignment warning at full_1c20.v(3013): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3013 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "26 23 full_1c20.v(3036) " "Warning: Verilog HDL assignment warning at full_1c20.v(3036): truncated value with size 26 to match size of target (23)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3036 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 full_1c20.v(3086) " "Warning: Verilog HDL assignment warning at full_1c20.v(3086): truncated value with size 32 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3086 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(3093) " "Warning: Verilog HDL assignment warning at full_1c20.v(3093): truncated value with size 32 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3093 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(3110) " "Warning: Verilog HDL assignment warning at full_1c20.v(3110): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 full_1c20.v(3146) " "Warning: Verilog HDL assignment warning at full_1c20.v(3146): truncated value with size 32 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3146 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 full_1c20.v(3228) " "Warning: Verilog HDL assignment warning at full_1c20.v(3228): truncated value with size 32 to match size of target (8)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3228 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(3350) " "Warning: Verilog HDL assignment warning at full_1c20.v(3350): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3350 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 full_1c20.v(3392) " "Warning: Verilog HDL assignment warning at full_1c20.v(3392): truncated value with size 32 to match size of target (16)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3392 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 3 full_1c20.v(3426) " "Warning: Verilog HDL assignment warning at full_1c20.v(3426): truncated value with size 24 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3426 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "high_res_timer.v 1 1 " "Info: Using design file high_res_timer.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 high_res_timer " "Info: Found entity 1: high_res_timer" {  } { { "high_res_timer.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/high_res_timer.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 high_res_timer.v(116) " "Warning: Verilog HDL assignment warning at high_res_timer.v(116): truncated value with size 2 to match size of target (1)" {  } { { "high_res_timer.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/high_res_timer.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 high_res_timer.v(141) " "Warning: Verilog HDL assignment warning at high_res_timer.v(141): truncated value with size 2 to match size of target (1)" {  } { { "high_res_timer.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/high_res_timer.v" 141 0 0 } }  } 0}