full_featured.map.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/alt_mac_out.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/alt_mac_out.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mac_out " "Info: Found entity 1: alt_mac_out" {  } { { "alt_mac_out.tdf" "" { Text "e:/altera/libraries/megafunctions/alt_mac_out.tdf" 209 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_ELABORATION_HEADER" "full_1c20:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add\|mult_add_ovq2:auto_generated\|alt_mac_out:mac_out2 " "Info: Issued messages during elaboration of megafunction \"full_1c20:inst\|cpu:the_cpu\|cpu_mult_cell:the_cpu_mult_cell\|altmult_add:the_altmult_add\|mult_add_ovq2:auto_generated\|alt_mac_out:mac_out2\"" {  } { { "db/mult_add_ovq2.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/mult_add_ovq2.tdf" 47 2 0 } }  } 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "clk " "Warning: Variable or input pin \"clk\" is defined but never used" {  } { { "alt_mac_out.tdf" "" { Text "e:/altera/libraries/megafunctions/alt_mac_out.tdf" 226 2 0 } } { "db/mult_add_ovq2.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/mult_add_ovq2.tdf" 47 2 0 } } { "altmult_add.tdf" "" { Text "e:/altera/libraries/megafunctions/altmult_add.tdf" 481 3 0 } } { "cpu_mult_cell.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_mult_cell.v" 29 -1 0 } } { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 9180 -1 0 } } { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 7412 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 544 760 1232 1408 "inst" "" } } } }  } 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "aclr " "Warning: Variable or input pin \"aclr\" is defined but never used" {  } { { "alt_mac_out.tdf" "" { Text "e:/altera/libraries/megafunctions/alt_mac_out.tdf" 227 2 0 } } { "db/mult_add_ovq2.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/mult_add_ovq2.tdf" 47 2 0 } } { "altmult_add.tdf" "" { Text "e:/altera/libraries/megafunctions/altmult_add.tdf" 481 3 0 } } { "cpu_mult_cell.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_mult_cell.v" 29 -1 0 } } { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 9180 -1 0 } } { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 7412 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 544 760 1232 1408 "inst" "" } } } }  } 0}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "ena " "Warning: Variable or input pin \"ena\" is defined but never used" {  } { { "alt_mac_out.tdf" "" { Text "e:/altera/libraries/megafunctions/alt_mac_out.tdf" 228 2 0 } } { "db/mult_add_ovq2.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/mult_add_ovq2.tdf" 47 2 0 } } { "altmult_add.tdf" "" { Text "e:/altera/libraries/megafunctions/altmult_add.tdf" 481 3 0 } } { "cpu_mult_cell.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_mult_cell.v" 29 -1 0 } } { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 9180 -1 0 } } { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 7412 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 544 760 1232 1408 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vkt1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vkt1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vkt1 " "Info: Found entity 1: altsyncram_vkt1" {  } { { "db/altsyncram_vkt1.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_vkt1.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gpm1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gpm1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gpm1 " "Info: Found entity 1: altsyncram_gpm1" {  } { { "db/altsyncram_gpm1.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_gpm1.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_jtag_debug_module_wrapper.v 1 1 " "Info: Using design file cpu_jtag_debug_module_wrapper.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module_wrapper " "Info: Found entity 1: cpu_jtag_debug_module_wrapper" {  } { { "cpu_jtag_debug_module_wrapper.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module_wrapper.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_jtag_debug_module.v 1 1 " "Info: Using design file cpu_jtag_debug_module.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_jtag_debug_module " "Info: Found entity 1: cpu_jtag_debug_module" {  } { { "cpu_jtag_debug_module.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "usr1 cpu_jtag_debug_module.v(314) " "Warning: Verilog HDL Always Construct warning at cpu_jtag_debug_module.v(314): variable \"usr1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpu_jtag_debug_module.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module.v" 314 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ena cpu_jtag_debug_module.v(314) " "Warning: Verilog HDL Always Construct warning at cpu_jtag_debug_module.v(314): variable \"ena\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpu_jtag_debug_module.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module.v" 314 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "usr1 cpu_jtag_debug_module.v(319) " "Warning: Verilog HDL Always Construct warning at cpu_jtag_debug_module.v(319): variable \"usr1\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpu_jtag_debug_module.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module.v" 319 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ena cpu_jtag_debug_module.v(319) " "Warning: Verilog HDL Always Construct warning at cpu_jtag_debug_module.v(319): variable \"ena\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "cpu_jtag_debug_module.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_jtag_debug_module.v" 319 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "custominstruction_cpu.v 1 1 " "Info: Using design file custominstruction_cpu.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 custominstruction_cpu " "Info: Found entity 1: custominstruction_cpu" {  } { { "custominstruction_cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/custominstruction_cpu.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(2151) " "Warning: Verilog HDL assignment warning at full_1c20.v(2151): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2151 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2197) " "Warning: Verilog HDL assignment warning at full_1c20.v(2197): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2197 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2222) " "Warning: Verilog HDL assignment warning at full_1c20.v(2222): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2222 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(2275) " "Warning: Verilog HDL assignment warning at full_1c20.v(2275): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2275 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 9 full_1c20.v(2307) " "Warning: Verilog HDL assignment warning at full_1c20.v(2307): truncated value with size 24 to match size of target (9)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2307 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "epcs_controller.v 3 3 " "Info: Using design file epcs_controller.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 epcs_controller_sub " "Info: Found entity 1: epcs_controller_sub" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 tornado_epcs_controller_atom " "Info: Found entity 2: tornado_epcs_controller_atom" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 427 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 epcs_controller " "Info: Found entity 3: epcs_controller" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 470 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 3 epcs_controller.v(545) " "Warning: Verilog HDL assignment warning at epcs_controller.v(545): truncated value with size 9 to match size of target (3)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 545 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 epcs_controller.v(546) " "Warning: Verilog HDL assignment warning at epcs_controller.v(546): truncated value with size 32 to match size of target (16)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 546 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 epcs_controller.v(312) " "Warning: Verilog HDL assignment warning at epcs_controller.v(312): truncated value with size 32 to match size of target (12)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 312 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 5 epcs_controller.v(326) " "Warning: Verilog HDL assignment warning at epcs_controller.v(326): truncated value with size 6 to match size of target (5)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 326 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 1 epcs_controller.v(332) " "Warning: Verilog HDL assignment warning at epcs_controller.v(332): truncated value with size 16 to match size of target (1)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 332 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 8 epcs_controller.v(364) " "Warning: Verilog HDL assignment warning at epcs_controller.v(364): truncated value with size 16 to match size of target (8)" {  } { { "epcs_controller.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/epcs_controller.v" 364 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ncq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ncq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ncq " "Info: Found entity 1: altsyncram_ncq" {  } { { "db/altsyncram_ncq.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_ncq.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(2621) " "Warning: Verilog HDL assignment warning at full_1c20.v(2621): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2621 0 0 } }  } 0}