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{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(1433) " "Warning: Verilog HDL assignment warning at full_1c20.v(1433): truncated value with size 2 to match size of target (1)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1433 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1724) " "Warning: Verilog HDL assignment warning at full_1c20.v(1724): truncated value with size 32 to match size of target (1)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1724 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1730) " "Warning: Verilog HDL assignment warning at full_1c20.v(1730): truncated value with size 32 to match size of target (1)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1730 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1733) " "Warning: Verilog HDL assignment warning at full_1c20.v(1733): truncated value with size 32 to match size of target (1)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1733 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 full_1c20.v(1795) " "Warning: Verilog HDL assignment warning at full_1c20.v(1795): truncated value with size 32 to match size of target (2)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1795 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 full_1c20.v(1804) " "Warning: Verilog HDL assignment warning at full_1c20.v(1804): truncated value with size 32 to match size of target (8)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1804 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 full_1c20.v(1817) " "Warning: Verilog HDL assignment warning at full_1c20.v(1817): truncated value with size 32 to match size of target (8)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1817 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 full_1c20.v(1830) " "Warning: Verilog HDL assignment warning at full_1c20.v(1830): truncated value with size 32 to match size of target (8)" { } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1830 0 0 } } } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu.v 30 30 " "Info: Using design file cpu.v, which is not specified as a design file for the current project, but contains definitions for 30 design units and 30 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_ic_data_module " "Info: Found entity 1: cpu_ic_data_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 26 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_ic_tag_module " "Info: Found entity 2: cpu_ic_tag_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 121 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_bht_module " "Info: Found entity 3: cpu_bht_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 218 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "4 cpu_register_bank_a_module " "Info: Found entity 4: cpu_register_bank_a_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 315 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_register_bank_b_module " "Info: Found entity 5: cpu_register_bank_b_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 412 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_dc_tag_module " "Info: Found entity 6: cpu_dc_tag_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 509 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_dc_data_module " "Info: Found entity 7: cpu_dc_data_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 590 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_nios2_oci_debug " "Info: Found entity 8: cpu_nios2_oci_debug" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 675 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "9 cpu_ociram_lpm_dram_bdp_component_module " "Info: Found entity 9: cpu_ociram_lpm_dram_bdp_component_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 787 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "10 cpu_nios2_ocimem " "Info: Found entity 10: cpu_nios2_ocimem" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 872 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "11 cpu_nios2_avalon_reg " "Info: Found entity 11: cpu_nios2_avalon_reg" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 997 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "12 cpu_nios2_oci_break " "Info: Found entity 12: cpu_nios2_oci_break" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 1199 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "13 cpu_nios2_oci_xbrk " "Info: Found entity 13: cpu_nios2_oci_xbrk" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 1669 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "14 cpu_nios2_oci_match_paired " "Info: Found entity 14: cpu_nios2_oci_match_paired" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 1953 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "15 cpu_nios2_oci_match_single " "Info: Found entity 15: cpu_nios2_oci_match_single" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 1983 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "16 cpu_nios2_oci_dbrk " "Info: Found entity 16: cpu_nios2_oci_dbrk" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2011 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "17 cpu_nios2_oci_itrace " "Info: Found entity 17: cpu_nios2_oci_itrace" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2228 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "18 cpu_nios2_oci_td_mode " "Info: Found entity 18: cpu_nios2_oci_td_mode" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2506 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "19 cpu_nios2_oci_dtrace " "Info: Found entity 19: cpu_nios2_oci_dtrace" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2565 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "20 cpu_nios2_oci_compute_tm_count " "Info: Found entity 20: cpu_nios2_oci_compute_tm_count" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2649 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "21 cpu_nios2_oci_fifowp_inc " "Info: Found entity 21: cpu_nios2_oci_fifowp_inc" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2712 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "22 cpu_nios2_oci_fifocount_inc " "Info: Found entity 22: cpu_nios2_oci_fifocount_inc" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2746 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "23 cpu_nios2_oci_fifo " "Info: Found entity 23: cpu_nios2_oci_fifo" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 2784 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "24 cpu_nios2_oci_pib " "Info: Found entity 24: cpu_nios2_oci_pib" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 3261 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "25 cpu_traceram_lpm_dram_bdp_component_module " "Info: Found entity 25: cpu_traceram_lpm_dram_bdp_component_module" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 3321 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "26 cpu_nios2_oci_im " "Info: Found entity 26: cpu_nios2_oci_im" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 3402 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "27 cpu_nios2_performance_monitor_counter " "Info: Found entity 27: cpu_nios2_performance_monitor_counter" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 3530 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "28 cpu_nios2_performance_monitors " "Info: Found entity 28: cpu_nios2_performance_monitors" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 3747 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "29 cpu_nios2_oci " "Info: Found entity 29: cpu_nios2_oci" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 4015 -1 0 } } } 0} { "Info" "ISGN_ENTITY_NAME" "30 cpu " "Info: Found entity 30: cpu" { } { { "cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu.v" 4693 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_test_bench.v 1 1 " "Info: Using design file cpu_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_test_bench " "Info: Found entity 1: cpu_test_bench" { } { { "cpu_test_bench.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_test_bench.v" 1 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" { } { { "altsyncram.tdf" "" { Text "e:/altera/libraries/megafunctions/altsyncram.tdf" 431 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vut.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vut.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vut " "Info: Found entity 1: altsyncram_vut" { } { { "db/altsyncram_vut.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_vut.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l701.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l701.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l701 " "Info: Found entity 1: altsyncram_l701" { } { { "db/altsyncram_l701.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_l701.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_erv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_erv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_erv " "Info: Found entity 1: altsyncram_erv" { } { { "db/altsyncram_erv.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_erv.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_otv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_otv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_otv " "Info: Found entity 1: altsyncram_otv" { } { { "db/altsyncram_otv.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_otv.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ptv.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ptv.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ptv " "Info: Found entity 1: altsyncram_ptv" { } { { "db/altsyncram_ptv.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_ptv.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fio1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fio1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fio1 " "Info: Found entity 1: altsyncram_fio1" { } { { "db/altsyncram_fio1.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_fio1.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_coo1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_coo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_coo1 " "Info: Found entity 1: altsyncram_coo1" { } { { "db/altsyncram_coo1.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/altsyncram_coo1.tdf" 40 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_mult_cell.v 1 1 " "Info: Using design file cpu_mult_cell.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_mult_cell " "Info: Found entity 1: cpu_mult_cell" { } { { "cpu_mult_cell.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/cpu_mult_cell.v" 1 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/altmult_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/altmult_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altmult_add " "Info: Found entity 1: altmult_add" { } { { "altmult_add.tdf" "" { Text "e:/altera/libraries/megafunctions/altmult_add.tdf" 301 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_ovq2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mult_add_ovq2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_ovq2 " "Info: Found entity 1: mult_add_ovq2" { } { { "db/mult_add_ovq2.tdf" "" { Text "F:/workspace/r_08_20/our_hardware_project/db/mult_add_ovq2.tdf" 30 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/alt_mac_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/alt_mac_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mac_mult " "Info: Found entity 1: alt_mac_mult" { } { { "alt_mac_mult.tdf" "" { Text "e:/altera/libraries/megafunctions/alt_mac_mult.tdf" 148 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" { } { { "lpm_mult.tdf" "" { Text "e:/altera/libraries/megafunctions/lpm_mult.tdf" 280 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" { } { { "multcore.tdf" "" { Text "e:/altera/libraries/megafunctions/multcore.tdf" 181 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/mul_lfrg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/mul_lfrg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mul_lfrg " "Info: Found entity 1: mul_lfrg" { } { { "mul_lfrg.tdf" "" { Text "e:/altera/libraries/megafunctions/mul_lfrg.tdf" 53 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" { } { { "mpar_add.tdf" "" { Text "e:/altera/libraries/megafunctions/mpar_add.tdf" 60 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "lpm_add_sub.tdf" "" { Text "e:/altera/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "addcore.tdf" "" { Text "e:/altera/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "a_csnbuffer.tdf" "" { Text "e:/altera/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
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