full_featured.map.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 20 14:26:47 2005 " "Info: Processing started: Sat Aug 20 14:26:47 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off full_featured -c full_featured " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off full_featured -c full_featured" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_featured.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_featured.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_featured " "Info: Found entity 1: full_featured" {  } { { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_IGNORED_ANONYMOUS_PORT" "unicode2char unicode2char.v(11) " "Warning: Verilog Module Declaration warning at unicode2char.v(11): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module \"unicode2char\"" {  } { { "our_CI/unicode2char.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/our_CI/unicode2char.v" 11 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "our_CI/unicode2char.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file our_CI/unicode2char.v" { { "Info" "ISGN_ENTITY_NAME" "1 unicode2char " "Info: Found entity 1: unicode2char" {  } { { "our_CI/unicode2char.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/our_CI/unicode2char.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "full_1c20.v 34 34 " "Info: Using design file full_1c20.v, which is not specified as a design file for the current project, but contains definitions for 34 design units and 34 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DSR_pio_s1_arbitrator " "Info: Found entity 1: DSR_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 alarm_pio_s1_arbitrator " "Info: Found entity 2: alarm_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 236 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 bswap_cpu_s1_arbitrator " "Info: Found entity 3: bswap_cpu_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 441 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 button_pio_s1_arbitrator " "Info: Found entity 4: button_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 480 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_jtag_debug_module_arbitrator " "Info: Found entity 5: cpu_jtag_debug_module_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 673 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_custom_instruction_master_arbitrator " "Info: Found entity 6: cpu_custom_instruction_master_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1047 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_data_master_arbitrator " "Info: Found entity 7: cpu_data_master_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1091 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_instruction_master_arbitrator " "Info: Found entity 8: cpu_instruction_master_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1596 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "9 custominstruction_cpu_s1_arbitrator " "Info: Found entity 9: custominstruction_cpu_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1955 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "10 epcs_controller_epcs_control_port_arbitrator " "Info: Found entity 10: epcs_controller_epcs_control_port_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1994 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "11 ext_ram_bus_avalon_slave_arbitrator " "Info: Found entity 11: ext_ram_bus_avalon_slave_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 2377 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "12 ext_ram_bus_bridge_arbitrator " "Info: Found entity 12: ext_ram_bus_bridge_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3237 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "13 high_res_timer_s1_arbitrator " "Info: Found entity 13: high_res_timer_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3245 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "14 jtag_uart_avalon_jtag_slave_arbitrator " "Info: Found entity 14: jtag_uart_avalon_jtag_slave_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3466 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "15 key_pio_s1_arbitrator " "Info: Found entity 15: key_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3717 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "16 lcd_ctrl_s1_arbitrator " "Info: Found entity 16: lcd_ctrl_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 3920 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "17 lcd_data_s1_arbitrator " "Info: Found entity 17: lcd_data_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4125 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "18 lcd_display_control_slave_arbitrator " "Info: Found entity 18: lcd_display_control_slave_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4337 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "19 led_pio_s1_arbitrator " "Info: Found entity 19: led_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4581 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "20 reconfig_request_pio_s1_arbitrator " "Info: Found entity 20: reconfig_request_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 4793 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "21 sdram_s1_arbitrator " "Info: Found entity 21: sdram_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 5006 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "22 seven_seg_pio_s1_arbitrator " "Info: Found entity 22: seven_seg_pio_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 5631 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "23 sys_clk_timer_s1_arbitrator " "Info: Found entity 23: sys_clk_timer_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 5836 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "24 sysid_control_slave_arbitrator " "Info: Found entity 24: sysid_control_slave_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 6057 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "25 uart1_s1_arbitrator " "Info: Found entity 25: uart1_s1_arbitrator" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 6244 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "26 reset_clk_domain_synch_module " "Info: Found entity 26: reset_clk_domain_synch_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 6489 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "27 full_1c20 " "Info: Found entity 27: full_1c20" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 6544 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "28 ext_flash_lane0_module " "Info: Found entity 28: ext_flash_lane0_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8058 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "29 ext_flash " "Info: Found entity 29: ext_flash" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8144 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "30 ext_ram_lane0_module " "Info: Found entity 30: ext_ram_lane0_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8191 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "31 ext_ram_lane1_module " "Info: Found entity 31: ext_ram_lane1_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8277 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "32 ext_ram_lane2_module " "Info: Found entity 32: ext_ram_lane2_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8363 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "33 ext_ram_lane3_module " "Info: Found entity 33: ext_ram_lane3_module" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8449 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "34 ext_ram " "Info: Found entity 34: ext_ram" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 8535 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(123) " "Warning: Verilog HDL assignment warning at full_1c20.v(123): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(165) " "Warning: Verilog HDL assignment warning at full_1c20.v(165): truncated value with size 32 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 165 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 2 full_1c20.v(199) " "Warning: Verilog HDL assignment warning at full_1c20.v(199): truncated value with size 24 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 199 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "DSR_pio.v 1 1 " "Info: Using design file DSR_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 DSR_pio " "Info: Found entity 1: DSR_pio" {  } { { "DSR_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/DSR_pio.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(328) " "Warning: Verilog HDL assignment warning at full_1c20.v(328): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 328 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 full_1c20.v(370) " "Warning: Verilog HDL assignment warning at full_1c20.v(370): truncated value with size 32 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 370 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 2 full_1c20.v(404) " "Warning: Verilog HDL assignment warning at full_1c20.v(404): truncated value with size 24 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 404 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "alarm_pio.v 1 1 " "Info: Using design file alarm_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 alarm_pio " "Info: Found entity 1: alarm_pio" {  } { { "alarm_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/alarm_pio.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "bswap_cpu.v 1 1 " "Info: Using design file bswap_cpu.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bswap_cpu " "Info: Found entity 1: bswap_cpu" {  } { { "bswap_cpu.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/bswap_cpu.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(567) " "Warning: Verilog HDL assignment warning at full_1c20.v(567): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 567 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 2 full_1c20.v(636) " "Warning: Verilog HDL assignment warning at full_1c20.v(636): truncated value with size 24 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 636 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "button_pio.v 1 1 " "Info: Using design file button_pio.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 button_pio " "Info: Found entity 1: button_pio" {  } { { "button_pio.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/button_pio.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 full_1c20.v(819) " "Warning: Verilog HDL assignment warning at full_1c20.v(819): truncated value with size 32 to match size of target (3)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 819 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(865) " "Warning: Verilog HDL assignment warning at full_1c20.v(865): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 865 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(890) " "Warning: Verilog HDL assignment warning at full_1c20.v(890): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 890 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "3 2 full_1c20.v(943) " "Warning: Verilog HDL assignment warning at full_1c20.v(943): truncated value with size 3 to match size of target (2)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 943 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "24 9 full_1c20.v(976) " "Warning: Verilog HDL assignment warning at full_1c20.v(976): truncated value with size 24 to match size of target (9)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 976 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 full_1c20.v(1009) " "Warning: Verilog HDL assignment warning at full_1c20.v(1009): truncated value with size 32 to match size of target (4)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1009 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1413) " "Warning: Verilog HDL assignment warning at full_1c20.v(1413): truncated value with size 32 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1413 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1419) " "Warning: Verilog HDL assignment warning at full_1c20.v(1419): truncated value with size 32 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1419 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 full_1c20.v(1422) " "Warning: Verilog HDL assignment warning at full_1c20.v(1422): truncated value with size 32 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1422 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 full_1c20.v(1431) " "Warning: Verilog HDL assignment warning at full_1c20.v(1431): truncated value with size 2 to match size of target (1)" {  } { { "full_1c20.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/full_1c20.v" 1431 0 0 } }  } 0}