full_featured.fit.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "PLD_CLOCKINPUT\[1\] " "Info: Promoted signal \"PLD_CLOCKINPUT\[1\]\" to use global clock" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "PLD_CLOCKINPUT\[1\]" } { 0 "PLD_CLOCKINPUT\[1\]" } } } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 376 312 480 392 "PLD_CLOCKINPUT\[1\]" "" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { PLD_CLOCKINPUT[1] } "NODE_NAME" } }  } 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "connector_pll:inst2\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"connector_pll:inst2\|altpll:altpll_component\|_clk0\" to use global clock" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "connector_pll:inst2\|altpll:altpll_component\|_clk0" } { 0 "connector_pll:inst2\|altpll:altpll_component\|_clk0" } } } } { "altpll.tdf" "" { Text "e:/altera/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { connector_pll:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { connector_pll:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~UPDATEUSER Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~UPDATEUSER\" to use Global clock" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ENET_INTRQ\[0\] Global clock " "Info: Automatically promoted signal \"ENET_INTRQ\[0\]\" to use Global clock" {  } { { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 712 520 688 728 "ENET_INTRQ\[0\]" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "ENET_INTRQ\[0\] " "Info: Pin \"ENET_INTRQ\[0\]\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 712 520 688 728 "ENET_INTRQ\[0\]" "" } } } } { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "ENET_INTRQ\[0\]" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { ENET_INTRQ[0] } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { ENET_INTRQ[0] } "NODE_NAME" } }  } 0}