full_featured.fit.qmsg

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 20 14:35:27 2005 " "Info: Processing started: Sat Aug 20 14:35:27 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off full_featured -c full_featured " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off full_featured -c full_featured" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "full_featured EP1C20F400C7 " "Info: Selected device EP1C20F400C7 for design \"full_featured\"" {  } {  } 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "sdram_pll:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"sdram_pll:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "sdram_pll:inst1\|altpll:altpll_component\|_extclk0 1 1 -63 -3499 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -63 degrees (-3499 ps) for sdram_pll:inst1\|altpll:altpll_component\|_extclk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "e:/altera/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "sdram_pll.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/sdram_pll.v" 93 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 120 840 1112 296 "inst1" "" } } } }  } 0}
{ "Critical Warning" "WCUT_CUT_YGR_PLL_MODE_CHANGED" "sdram_pll:inst1\|altpll:altpll_component\|pll Zero delay buffer " "Critical Warning: Changed operation mode of PLL \"sdram_pll:inst1\|altpll:altpll_component\|pll\" to Zero delay buffer" {  } { { "altpll.tdf" "" { Text "e:/altera/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "sdram_pll.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/sdram_pll.v" 93 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 120 840 1112 296 "inst1" "" } } } }  } 1}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "connector_pll:inst2\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"connector_pll:inst2\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "connector_pll:inst2\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for connector_pll:inst2\|altpll:altpll_component\|_clk0 port" {  } {  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "connector_pll:inst2\|altpll:altpll_component\|_extclk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for connector_pll:inst2\|altpll:altpll_component\|_extclk0 port" {  } {  } 0}  } { { "altpll.tdf" "" { Text "e:/altera/libraries/megafunctions/altpll.tdf" 723 3 0 } } { "connector_pll.v" "" { Text "F:/workspace/r_08_20/our_hardware_project/connector_pll.v" 94 -1 0 } } { "full_featured.bdf" "" { Schematic "F:/workspace/r_08_20/our_hardware_project/full_featured.bdf" { { 320 840 1112 504 "inst2" "" } } } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F400C7 " "Info: Device EP1C4F400C7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F400I7 " "Info: Device EP1C4F400I7 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C20F400I7 " "Info: Device EP1C20F400I7 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 213 " "Info: No exact pin location assignment(s) for 4 pins of 213 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "e:/altera/bin/Assignment Editor.qase" "" { Assignment "e:/altera/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" "" { Report "F:/workspace/r_08_20/our_hardware_project/db/full_featured_cmp.qrpt" Compiler "full_featured" "UNKNOWN" "V1" "F:/workspace/r_08_20/our_hardware_project/db/full_featured.quartus_db" { Floorplan "F:/workspace/r_08_20/our_hardware_project/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" { Floorplan "F:/workspace/r_08_20/our_hardware_project/full_featured.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}