full_featured.hif

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
e:|altera|libraries|megafunctions|stratix_ram_block.inc
1094871114
e:|altera|libraries|megafunctions|lpm_mux.inc
1094870318
e:|altera|libraries|megafunctions|lpm_decode.inc
1094870100
e:|altera|libraries|megafunctions|aglobal42.inc
1101745276
e:|altera|libraries|megafunctions|altsyncram.inc
1094868954
e:|altera|libraries|megafunctions|a_rdenreg.inc
1094867530
e:|altera|libraries|megafunctions|altrom.inc
1094868876
e:|altera|libraries|megafunctions|altram.inc
1094868838
e:|altera|libraries|megafunctions|altdpram.inc
1094868494
e:|altera|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_ptv
# case_insensitive
# source_file
db|altsyncram_ptv.tdf
1124516926
6
# storage
db|full_featured.(30).cnf
db|full_featured.(30).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
}
# memory_file {
rf_ram_b.mif
1124516394
}
# end
# entity
cpu_dc_tag_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
1124516428
7
# storage
db|full_featured.(31).cnf
db|full_featured.(31).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
lpm_file
dc_tag_ram.mif
PARAMETER_STRING
USR
}
# end
# entity
altsyncram
# case_insensitive
# source_file
e:|altera|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|full_featured.(32).cnf
db|full_featured.(32).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
17
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
17
PARAMETER_DEC
USR
WIDTHAD_B
9
PARAMETER_DEC
USR
NUMWORDS_B
512
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
dc_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_fio1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
wren_b
}
# include_file {
e:|altera|libraries|megafunctions|stratix_ram_block.inc
1094871114
e:|altera|libraries|megafunctions|lpm_mux.inc
1094870318
e:|altera|libraries|megafunctions|lpm_decode.inc
1094870100
e:|altera|libraries|megafunctions|aglobal42.inc
1101745276
e:|altera|libraries|megafunctions|altsyncram.inc
1094868954
e:|altera|libraries|megafunctions|a_rdenreg.inc
1094867530
e:|altera|libraries|megafunctions|altrom.inc
1094868876
e:|altera|libraries|megafunctions|altram.inc
1094868838
e:|altera|libraries|megafunctions|altdpram.inc
1094868494
e:|altera|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_fio1
# case_insensitive
# source_file
db|altsyncram_fio1.tdf
1124516926
6
# storage
db|full_featured.(33).cnf
db|full_featured.(33).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
data_b16
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
clock0
clock1
clocken0
clocken1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_a16
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
}
# memory_file {
dc_tag_ram.mif
1124516396
}
# end
# entity
cpu_dc_data_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu.v
1124516428
7
# storage
db|full_featured.(34).cnf
db|full_featured.(34).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# end
# entity
altsyncram
# case_insensitive
# source_file
e:|altera|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|full_featured.(35).cnf
db|full_featured.(35).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
9
PARAMETER_DEC
USR
NUMWORDS_B
512
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
4
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_coo1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
byteena_b
byteena_b
byteena_b
byteena_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
wren_b
}
# include_file {
e:|altera|libraries|megafunctions|stratix_ram_block.inc
1094871114
e:|altera|libraries|megafunctions|lpm_mux.inc
1094870318
e:|altera|libraries|megafunctions|lpm_decode.inc
1094870100
e:|altera|libraries|megafunctions|aglobal42.inc
1101745276
e:|altera|libraries|megafunctions|altsyncram.inc
1094868954
e:|altera|libraries|megafunctions|a_rdenreg.inc
1094867530
e:|altera|libraries|megafunctions|altrom.inc
1094868876
e:|altera|libraries|megafunctions|altram.inc
1094868838
e:|altera|libraries|megafunctions|altdpram.inc
1094868494
e:|altera|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
cpu_mult_cell
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_mult_cell.v
1124516412
7
# storage
db|full_featured.(37).cnf
db|full_featured.(37).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION