altsyncram_ncq.tdf

来自「基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势」· TDF 代码 · 共 661 行 · 第 1/2 页

TDF
661 行
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12
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a16 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a17 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a18 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a19 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a20 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a21 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a22 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a23 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a24 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a25 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a26 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a27 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a30 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a31 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "epcs_controller_boot_rom.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "rom",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			RAM_BLOCK_TYPE = "auto"
		);

BEGIN 
	ram_block1a[31..0].clk0 = clock0;
	ram_block1a[0].portaaddr[] = ( address_a[6..0]);
	ram_block1a[1].portaaddr[] = ( address_a[6..0]);
	ram_block1a[2].portaaddr[] = ( address_a[6..0]);
	ram_block1a[3].portaaddr[] = ( address_a[6..0]);
	ram_block1a[4].portaaddr[] = ( address_a[6..0]);
	ram_block1a[5].portaaddr[] = ( address_a[6..0]);
	ram_block1a[6].portaaddr[] = ( address_a[6..0]);
	ram_block1a[7].portaaddr[] = ( address_a[6..0]);
	ram_block1a[8].portaaddr[] = ( address_a[6..0]);
	ram_block1a[9].portaaddr[] = ( address_a[6..0]);
	ram_block1a[10].portaaddr[] = ( address_a[6..0]);
	ram_block1a[11].portaaddr[] = ( address_a[6..0]);
	ram_block1a[12].portaaddr[] = ( address_a[6..0]);
	ram_block1a[13].portaaddr[] = ( address_a[6..0]);
	ram_block1a[14].portaaddr[] = ( address_a[6..0]);
	ram_block1a[15].portaaddr[] = ( address_a[6..0]);
	ram_block1a[16].portaaddr[] = ( address_a[6..0]);
	ram_block1a[17].portaaddr[] = ( address_a[6..0]);
	ram_block1a[18].portaaddr[] = ( address_a[6..0]);
	ram_block1a[19].portaaddr[] = ( address_a[6..0]);
	ram_block1a[20].portaaddr[] = ( address_a[6..0]);
	ram_block1a[21].portaaddr[] = ( address_a[6..0]);
	ram_block1a[22].portaaddr[] = ( address_a[6..0]);
	ram_block1a[23].portaaddr[] = ( address_a[6..0]);
	ram_block1a[24].portaaddr[] = ( address_a[6..0]);
	ram_block1a[25].portaaddr[] = ( address_a[6..0]);
	ram_block1a[26].portaaddr[] = ( address_a[6..0]);
	ram_block1a[27].portaaddr[] = ( address_a[6..0]);
	ram_block1a[28].portaaddr[] = ( address_a[6..0]);
	ram_block1a[29].portaaddr[] = ( address_a[6..0]);
	ram_block1a[30].portaaddr[] = ( address_a[6..0]);
	ram_block1a[31].portaaddr[] = ( address_a[6..0]);
	q_a[] = ( ram_block1a[31].portadataout[0..0], ram_block1a[30].portadataout[0..0], ram_block1a[29].portadataout[0..0], ram_block1a[28].portadataout[0..0], ram_block1a[27].portadataout[0..0], ram_block1a[26].portadataout[0..0], ram_block1a[25].portadataout[0..0], ram_block1a[24].portadataout[0..0], ram_block1a[23].portadataout[0..0], ram_block1a[22].portadataout[0..0], ram_block1a[21].portadataout[0..0], ram_block1a[20].portadataout[0..0], ram_block1a[19].portadataout[0..0], ram_block1a[18].portadataout[0..0], ram_block1a[17].portadataout[0..0], ram_block1a[16].portadataout[0..0], ram_block1a[15].portadataout[0..0], ram_block1a[14].portadataout[0..0], ram_block1a[13].portadataout[0..0], ram_block1a[12].portadataout[0..0], ram_block1a[11].portadataout[0..0], ram_block1a[10].portadataout[0..0], ram_block1a[9].portadataout[0..0], ram_block1a[8].portadataout[0..0], ram_block1a[7].portadataout[0..0], ram_block1a[6].portadataout[0..0], ram_block1a[5].portadataout[0..0], ram_block1a[4].portadataout[0..0], ram_block1a[3].portadataout[0..0], ram_block1a[2].portadataout[0..0], ram_block1a[1].portadataout[0..0], ram_block1a[0].portadataout[0..0]);
END;
--VALID FILE
12

altsyncram_ncq.tdf - 源码说明

本页面展示了「基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势」中的 altsyncram_ncq.tdf 源码文件，采用 TDF 编程语言编写，共 661 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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