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-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
---------------------------------------------------------------------------------
Quartus II Version 4.2 Build 157 12/07/2004 SJ Full Version
CHIP "full_featured" ASSIGNED TO AN: EP1C20F400C7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
VCCINT : A2 : power : : 1.5V : :
GND : A3 : gnd : : : :
FSE_A[1] : A4 : output : LVTTL : : 2 : Y
VCCIO2 : A5 : power : : 3.3V : 2 :
FSE_D[3] : A6 : bidir : LVTTL : : 2 : Y
FSE_D[7] : A7 : bidir : LVTTL : : 2 : Y
FSE_D[13] : A8 : bidir : LVTTL : : 2 : Y
FSE_D[17] : A9 : bidir : LVTTL : : 2 : Y
FSE_D[23] : A10 : bidir : LVTTL : : 2 : Y
FSE_D[30] : A11 : bidir : LVTTL : : 2 : Y
FLASH_CS_N : A12 : output : LVTTL : : 2 : Y
RESERVED_INPUT : A13 : : : : 2 :
RESERVED_INPUT : A14 : : : : 2 :
RESERVED_INPUT : A15 : : : : 2 :
VCCIO2 : A16 : power : : 3.3V : 2 :
RESERVED_INPUT : A17 : : : : 2 :
GND : A18 : gnd : : : :
VCCINT : A19 : power : : 1.5V : :
GND : A20 : gnd : : : :
VCCINT : B1 : power : : 1.5V : :
GND : B2 : gnd : : : :
LEDG[6] : B3 : output : LVTTL : : 2 : Y
FSE_A[0] : B4 : output : LVTTL : : 2 : Y
FSE_A[5] : B5 : output : LVTTL : : 2 : Y
FSE_D[2] : B6 : bidir : LVTTL : : 2 : Y
FSE_D[6] : B7 : bidir : LVTTL : : 2 : Y
FSE_D[12] : B8 : bidir : LVTTL : : 2 : Y
FSE_D[16] : B9 : bidir : LVTTL : : 2 : Y
FSE_D[22] : B10 : bidir : LVTTL : : 2 : Y
FSE_D[29] : B11 : bidir : LVTTL : : 2 : Y
FLASH_OE_N : B12 : output : LVTTL : : 2 : Y
RESERVED_INPUT : B13 : : : : 2 :
LEDG[7] : B14 : output : LVTTL : : 2 : Y
RESERVED_INPUT : B15 : : : : 2 :
RESERVED_INPUT : B16 : : : : 2 :
RESERVED_INPUT : B17 : : : : 2 :
RESERVED_INPUT : B18 : : : : 2 :
GND : B19 : gnd : : : :
VCCINT : B20 : power : : 1.5V : :
GND : C1 : gnd : : : :
FSE_A[6] : C2 : output : LVTTL : : 1 : Y
RESERVED_INPUT : C3 : : : : 1 :
PLD_CLEAR_N : C4 : input : LVTTL : : 2 : Y
FSE_A[4] : C5 : output : LVTTL : : 2 : Y
FSE_D[0] : C6 : bidir : LVTTL : : 2 : Y
FSE_D[9] : C7 : bidir : LVTTL : : 2 : Y
FSE_D[15] : C8 : bidir : LVTTL : : 2 : Y
FSE_D[19] : C9 : bidir : LVTTL : : 2 : Y
FSE_D[25] : C10 : bidir : LVTTL : : 2 : Y
FSE_D[27] : C11 : bidir : LVTTL : : 2 : Y
RESERVED_INPUT : C12 : : : : 2 :
RESERVED_INPUT : C13 : : : : 2 :
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