📄 full_1c20.ptf
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type = "dataa";
}
PORT datab
{
width = "32";
direction = "input";
type = "datab";
}
PORT result
{
width = "32";
direction = "output";
type = "result";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "0";
Base_Address = "0x00000000";
Is_Custom_Instruction = "1";
Is_Visible = "0";
IRQ_MASTER cpu/custom_instruction_master
{
IRQ_Number = "NC";
}
MASTERED_BY cpu/custom_instruction_master
{
priority = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Is_Visible = "0";
Instantiate_In_System_Module = "1";
Is_Custom_Instruction = "1";
View
{
MESSAGES
{
}
}
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
Module_Name = "bitswap_instruction_unit";
Synthesize_Imported_HDL = "1";
ci_macro_name = "bit_swap1";
ci_operands = "1";
ci_cycles = "1";
ci_has_prefix = "0";
ci_inst_type = "combinatorial";
}
PORT_WIRING
{
}
}
MODULE ext_ram_bus
{
class = "altera_avalon_tri_state_bridge";
class_version = "2.0";
SLAVE avalon_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Register_Outgoing_Signals = "1";
Register_Incoming_Signals = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Bridges_To = "avalon_slave";
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Is_Bridge = "1";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
}
Clock_Source = "clk";
}
}
MODULE ext_flash
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "23";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
flash_reference_designator = "U5";
Supports_Flash_File_System = "1";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "23";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
Simulation_Num_Lanes = "1";
Is_Nonvolatile_Storage = "1";
Address_Span = "8388608";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Convert_Xs_To_0 = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Make_Memory_Model = "1";
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "8388608";
MAKE
{
TARGET flashfiles
{
ext_flash
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Dependency = "$(ELF)";
Target_File = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Command2 = "elf2flash --input=$(ELF) --flash=U5 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER) --outfile=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
}
}
TARGET programflash
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash";
Target_File = "ext_flash_programflash";
Is_Phony = "1";
}
}
TARGET factory
{
ext_flash
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U5 --offset=0x700000 --output=factory.flash $(SOF) ";
Command2 = "nios2-flash-programmer --input=factory.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "";
Is_Phony = "1";
Target_File = "ext_flash_factory_configuration";
}
}
MACRO
{
EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(EXT_FLASH_FLASHTARGET_TMP1:0=)";
EXT_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET sim
{
ext_flash
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
TARGET delete_placeholder_warning
{
ext_flash
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET user
{
ext_flash
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U5 --offset=0x600000 --output=user.flash $(SOF) ";
Command2 = "nios2-flash-programmer --input=user.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Dependency = "";
Is_Phony = "1";
Target_File = "ext_flash_user_configuration";
}
}
TARGET programflashnoelfdependency
{
ext_flash
{
All_Depends_On = "0";
Command1 = "nios2-flash-programmer --input=$(EXT_FLASH_FLASHTARGET_ALT_SIM_PREFIX)ext_flash.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --base=0x00800000 ";
Is_Phony = "1";
Target_File = "ext_flash_programflashnoelf";
}
}
}
contents_info = "SIMDIR/ext_flash.dat 1079724509 ";
}
}
MODULE ext_ram
{
class = "altera_nios_dev_kit_stratix_edition_sram2";
class_version = "1.0";
iss_model_name = "altera_memory";
HDL_INFO
{
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1024";
sram_memory_units = "1024";
sram_data_width = "32";
MAKE
{
TARGET sim
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
TARGET delete_placeholder_warning
{
ext_ram
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
}
contents_info = "SIMDIR/ext_ram_lane0.dat 1079724513 SIMDIR/ext_ram_lane1.dat 1079724513 SIMDIR/ext_ram_lane2.dat 1079724513 SIMDIR/ext_ram_lane3.dat 1079724513 SIMDIR/ext_ram.dat 1079724513 ";
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT be_n
{
width = "4";
is_shared = "0";
direction = "input";
type = "byteenable_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
Read_Wait_States = "0ns";
Write_Wait_States = "0ns";
Hold_Time = "half";
Base_Address = "0x02000000";
Address_Span = "1048576";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Setup_Time = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
}
}
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