full_featured.tan.rpt

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+------------------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+
; Type                                                             ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                                                           ; To                                                                                                             ; From Clock                                        ; To Clock                                          ; Failed Paths ;
+------------------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+
; Worst-case tsu                                                   ; N/A       ; None                             ; 15.291 ns                                      ; LCD[0]                                                                                                         ; full_1c20:inst|cpu:the_cpu|d_readdata_d1[0]                                                                    ;                                                   ; PLD_CLOCKINPUT[1]                                 ; 0            ;
; Worst-case tco                                                   ; N/A       ; None                             ; 17.445 ns                                      ; full_1c20:inst|cpu:the_cpu|d_address[18]                                                                       ; LCD_E                                                                                                          ; PLD_CLOCKINPUT[1]                                 ;                                                   ; 0            ;
; Worst-case tpd                                                   ; N/A       ; None                             ; 1.879 ns                                       ; altera_internal_jtag~TDO                                                                                       ; altera_reserved_tdo                                                                                            ;                                                   ;                                                   ; 0            ;
; Worst-case th                                                    ; N/A       ; None                             ; 1.719 ns                                       ; altera_internal_jtag                                                                                           ; full_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|wdata[0]                  ;                                                   ; altera_internal_jtag~TCKUTAP                      ; 0            ;
; Clock Setup: 'connector_pll:inst2|altpll:altpll_component|_clk0' ; 2.825 ns  ; 50.00 MHz ( period = 20.000 ns ) ; 58.22 MHz ( period = 17.175 ns )               ; full_1c20:inst|cpu:the_cpu|E_src1[5]                                                                           ; full_1c20:inst|cpu:the_cpu|E_src1[14]                                                                          ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'PLD_CLOCKINPUT[1]'                                 ; 15.942 ns ; 50.00 MHz ( period = 20.000 ns ) ; 246.43 MHz ( period = 4.058 ns )               ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[5] ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0] ; PLD_CLOCKINPUT[1]                                 ; PLD_CLOCKINPUT[1]                                 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                      ; N/A       ; None                             ; 81.49 MHz ( period = 12.272 ns )               ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]                                                                    ; full_1c20:inst|jtag_uart:the_jtag_uart|alt_jtag_atlantic:jtag_uart_alt_jtag_atlantic|jupdate                   ; altera_internal_jtag~TCKUTAP                      ; altera_internal_jtag~TCKUTAP                      ; 0            ;
; Clock Setup: 'ENET_INTRQ[0]'                                     ; N/A       ; None                             ; Restricted to 320.10 MHz ( period = 3.124 ns ) ; full_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib|x2          ; full_1c20:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_pib:the_cpu_nios2_oci_pib|tr_clk_reg  ; ENET_INTRQ[0]                                     ; ENET_INTRQ[0]                                     ; 0            ;
; Clock Hold: 'connector_pll:inst2|altpll:altpll_component|_clk0'  ; 0.727 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; full_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[1]                                                                ; full_1c20:inst|cpu:the_cpu|ic_fill_dp_offset[1]                                                                ; connector_pll:inst2|altpll:altpll_component|_clk0 ; connector_pll:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'PLD_CLOCKINPUT[1]'                                  ; 1.161 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                                            ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0] ; delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0] ; PLD_CLOCKINPUT[1]                                 ; PLD_CLOCKINPUT[1]                                 ; 0            ;
; Total number of failed paths                                     ;           ;                                  ;                                                ;                                                                                                                ;                                                                                                                ;                                                   ;                                                   ; 0            ;
+------------------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------+---------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C20F400C7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+