📄 bswap_cpu.v
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//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera. Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to
//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
//their respective licensors. No other licenses, including any licenses
//needed under any third party's intellectual property, are provided herein.
//Copying or modifying any file, or portion thereof, to which this notice
//is attached violates this copyright.
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module bswap_cpu (
// inputs:
dataa,
datab,
// outputs:
result
);
output [ 31: 0] result;
input [ 31: 0] dataa;
input [ 31: 0] datab;
wire [ 31: 0] result;
assign result[31] = dataa[0];
assign result[30] = dataa[1];
assign result[29] = dataa[2];
assign result[28] = dataa[3];
assign result[27] = dataa[4];
assign result[26] = dataa[5];
assign result[25] = dataa[6];
assign result[24] = dataa[7];
assign result[23] = dataa[8];
assign result[22] = dataa[9];
assign result[21] = dataa[10];
assign result[20] = dataa[11];
assign result[19] = dataa[12];
assign result[18] = dataa[13];
assign result[17] = dataa[14];
assign result[16] = dataa[15];
assign result[15] = dataa[16];
assign result[14] = dataa[17];
assign result[13] = dataa[18];
assign result[12] = dataa[19];
assign result[11] = dataa[20];
assign result[10] = dataa[21];
assign result[9] = dataa[22];
assign result[8] = dataa[23];
assign result[7] = dataa[24];
assign result[6] = dataa[25];
assign result[5] = dataa[26];
assign result[4] = dataa[27];
assign result[3] = dataa[28];
assign result[2] = dataa[29];
assign result[1] = dataa[30];
assign result[0] = dataa[31];
endmodule
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