full_featured.map.rpt

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Aug 20 14:35:15 2005    ;
; Quartus II Version          ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name               ; full_featured                            ;
; Top-level Entity Name       ; full_featured                            ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 9,512                                    ;
; Total pins                  ; 213                                      ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 81,152                                   ;
; Total PLLs                  ; 2                                        ;
+-----------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                      ;
+--------------------------------------------------------------------+---------------+---------------+
; Option                                                             ; Setting       ; Default Value ;
+--------------------------------------------------------------------+---------------+---------------+
; Device                                                             ; EP1C20F400C7  ;               ;
; Family name                                                        ; Cyclone       ; Stratix       ;
; Type of Retiming Performed During Resynthesis                      ; Full          ;               ;
; Resynthesis Optimization Effort                                    ; Normal        ;               ;
; Physical Synthesis Level for Resynthesis                           ; Normal        ;               ;
; Use Generated Physical Constraints File                            ; On            ;               ;
; Use smart compilation                                              ; Normal        ; Normal        ;
; Restructure Multiplexers                                           ; Auto          ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off           ; off           ;
; Preserve fewer node names                                          ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off           ; Off           ;
; Verilog Version                                                    ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93        ; VHDL93        ;
; Top-level entity name                                              ; full_featured ; full_featured ;
; State Machine Processing                                           ; Auto          ; Auto          ;
; Extract Verilog State Machines                                     ; On            ; On            ;
; Extract VHDL State Machines                                        ; On            ; On            ;
; NOT Gate Push-Back                                                 ; On            ; On            ;
; Power-Up Don't Care                                                ; On            ; On            ;
; Remove Redundant Logic Cells                                       ; Off           ; Off           ;
; Remove Duplicate Registers                                         ; On            ; On            ;
; Ignore CARRY Buffers                                               ; Off           ; Off           ;
; Ignore CASCADE Buffers                                             ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                              ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                          ; Off           ; Off           ;
; Ignore LCELL Buffers                                               ; Off           ; Off           ;
; Ignore SOFT Buffers                                                ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                                     ; Off           ; Off           ;
; Optimization Technique -- Cyclone                                  ; Balanced      ; Balanced      ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70            ; 70            ;
; Auto Carry Chains                                                  ; On            ; On            ;
; Auto Open-Drain Pins                                               ; On            ; On            ;
; Remove Duplicate Logic                                             ; On            ; On            ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off           ; Off           ;
; Perform gate-level register retiming                               ; Off           ; Off           ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On            ; On            ;