dma.v

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

      if (reset_n == 0)
          fifo_full <= 0;
      else if (clk_en)
          fifo_full <= p1_fifo_full;
    end


  assign write_collision = fifo_write && (wraddress == rdaddress);
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_write_data <= 0;
      else if (write_collision)
          last_write_data <= fifo_wr_data;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_write_collision <= 0;
      else if (1)
          if (write_collision)
              last_write_collision <= -1;
          else if (fifo_read)
              last_write_collision <= 0;
    end


  assign fifo_rd_data = last_write_collision ? last_write_data : fifo_ram_q;
  dma_fifo_module_fifo_ram_module dma_fifo_module_fifo_ram
    (
      .clk       (clk),
      .data      (fifo_wr_data),
      .q         (fifo_ram_q),
      .rdaddress (rdaddress),
      .rdclken   (1'b1),
      .reset_n   (reset_n),
      .wraddress (wraddress),
      .wrclock   (clk),
      .wren      (fifo_write)
    );



endmodule


module dma_mem_read (
                      // inputs:
                       clk,
                       clk_en,
                       go,
                       p1_done_read,
                       p1_fifo_full,
                       read_waitrequest,
                       reset_n,

                      // outputs:
                       inc_read,
                       mem_read_n,
                       read_select
                    );

  output           inc_read;
  output           mem_read_n;
  output           read_select;
  input            clk;
  input            clk_en;
  input            go;
  input            p1_done_read;
  input            p1_fifo_full;
  input            read_waitrequest;
  input            reset_n;

  reg              dma_mem_read_access;
  reg              dma_mem_read_idle;
  wire             inc_read;
  wire             mem_read_n;
  wire             p1_read_select;
  reg              read_select;
  assign mem_read_n = ~read_select;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          read_select <= 0;
      else if (clk_en)
          read_select <= p1_read_select;
    end


  assign inc_read = read_select & ~read_waitrequest;
  // Transitions into state 'idle'.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dma_mem_read_idle <= 1;
      else if (clk_en)
          dma_mem_read_idle <= ((dma_mem_read_idle == 1) & (go == 0)) |
                    ((dma_mem_read_idle == 1) & (p1_done_read == 1)) |
                    ((dma_mem_read_idle == 1) & (p1_fifo_full == 1)) |
                    ((dma_mem_read_access == 1) & (read_waitrequest == 0) & (p1_fifo_full == 1)) |
                    ((dma_mem_read_access == 1) & (p1_done_read == 1) & (read_waitrequest == 0));

    end


  // Transitions into state 'access'.
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dma_mem_read_access <= 0;
      else if (clk_en)
          dma_mem_read_access <= ((dma_mem_read_idle == 1) & (p1_done_read == 0) & (go == 1) & (p1_fifo_full == 0)) |
                    ((dma_mem_read_access == 1) & (read_waitrequest == 1)) |
                    ((dma_mem_read_access == 1) & (p1_done_read == 0) & (read_waitrequest == 0) & (p1_fifo_full == 0));

    end


  assign p1_read_select = ({1 {((dma_mem_read_access && (read_waitrequest == 1)))}} & 1) |
    ({1 {((dma_mem_read_access && (p1_done_read == 0) && (p1_fifo_full == 0) && (read_waitrequest == 0)))}} & 1) |
    ({1 {((dma_mem_read_idle && (go == 1) && (p1_done_read == 0) && (p1_fifo_full == 0)))}} & 1);



endmodule


module dma_mem_write (
                       // inputs:
                        d1_enabled_write_endofpacket,
                        fifo_datavalid,
                        write_waitrequest,

                       // outputs:
                        fifo_read,
                        inc_write,
                        mem_write_n,
                        write_select
                     );

  output           fifo_read;
  output           inc_write;
  output           mem_write_n;
  output           write_select;
  input            d1_enabled_write_endofpacket;
  input            fifo_datavalid;
  input            write_waitrequest;

  wire             fifo_read;
  wire             inc_write;
  wire             mem_write_n;
  wire             write_select;
  assign write_select = fifo_datavalid & ~d1_enabled_write_endofpacket;
  assign mem_write_n = ~write_select;
  assign fifo_read = write_select & ~write_waitrequest;
  assign inc_write = fifo_read;


endmodule


// DMA peripheral dma
//Mastered by:
//cpu/data_master; 
//Read slaves:
//sdram/s1; lan91c111/s1; ext_flash/s1; ext_ram/s1; 
//Write slaves:
//sdram/s1; lan91c111/s1; ext_flash/s1; ext_ram/s1; 


module dma (
             // inputs:
              clk,
              dma_ctl_address,
              dma_ctl_chipselect,
              dma_ctl_write_n,
              dma_ctl_writedata,
              read_endofpacket,
              read_readdata,
              read_readdatavalid,
              read_waitrequest,
              reset_n,
              write_endofpacket,
              write_waitrequest,

             // outputs:
              dma_ctl_irq,
              dma_ctl_readdata,
              dma_ctl_readyfordata,
              read_address,
              read_chipselect,
              read_flush,
              read_read_n,
              write_address,
              write_byteenable,
              write_chipselect,
              write_write_n,
              write_writedata
           );

  output           dma_ctl_irq;
  output  [ 25: 0] dma_ctl_readdata;
  output           dma_ctl_readyfordata;
  output  [ 25: 0] read_address;
  output           read_chipselect;
  output           read_flush;
  output           read_read_n;
  output  [ 25: 0] write_address;
  output  [  3: 0] write_byteenable;
  output           write_chipselect;
  output           write_write_n;
  output  [ 31: 0] write_writedata;
  input            clk;
  input   [  2: 0] dma_ctl_address;
  input            dma_ctl_chipselect;
  input            dma_ctl_write_n;
  input   [ 25: 0] dma_ctl_writedata;
  input            read_endofpacket;
  input   [ 31: 0] read_readdata;
  input            read_readdatavalid;
  input            read_waitrequest;
  input            reset_n;
  input            write_endofpacket;
  input            write_waitrequest;

  wire             busy;
  wire             byte;
  wire             clk_en;
  reg     [ 11: 0] control;
  reg              d1_done_transaction;
  reg              d1_enabled_write_endofpacket;
  reg              d1_read_got_endofpacket;
  wire             dma_ctl_irq;
  reg     [ 25: 0] dma_ctl_readdata;
  wire             dma_ctl_readyfordata;
  reg              done;
  wire             done_transaction;
  reg              done_write;
  wire             doubleword;
  wire             enabled_write_endofpacket;
  wire             fifo_datavalid;
  wire             fifo_empty;
  wire    [ 31: 0] fifo_rd_data;
  wire    [ 31: 0] fifo_rd_data_as_byte;
  wire    [ 31: 0] fifo_rd_data_as_hw;
  wire    [ 31: 0] fifo_rd_data_as_word;
  wire             fifo_read;
  wire    [ 31: 0] fifo_wr_data;
  wire             fifo_write;
  wire             fifo_write_data_valid;
  wire             flush_fifo;
  wire             go;
  wire             hw;
  wire             i_en;
  wire             inc_read;
  wire             inc_write;
  wire             leen;
  reg              len;
  reg     [ 24: 0] length;
  reg              length_eq_0;
  wire             mem_read_n;
  wire             mem_write_n;
  wire    [ 11: 0] p1_control;
  wire    [ 25: 0] p1_dma_ctl_readdata;
  wire             p1_done_read;
  wire             p1_done_write;
  wire             p1_fifo_full;
  wire    [ 24: 0] p1_length;
  wire             p1_length_eq_0;
  wire             p1_read_got_endofpacket;
  wire    [ 25: 0] p1_readaddress;
  wire             p1_write_got_endofpacket;
  wire    [ 25: 0] p1_writeaddress;
  wire    [ 24: 0] p1_writelength;
  wire             p1_writelength_eq_0;
  wire             quadword;
  wire             rcon;
  wire    [ 25: 0] read_address;
  wire             read_chipselect;
  wire             read_flush;
  reg              read_got_endofpacket;
  wire             read_read_n;
  wire             read_select;
  reg     [ 25: 0] readaddress;
  wire    [  4: 0] readaddress_inc;
  wire             reen;
  reg              reop;
  wire    [  4: 0] status;
  wire             status_register_write;
  wire             wcon;
  wire             ween;
  reg              weop;
  wire             word;
  wire    [ 25: 0] write_address;
  wire    [  3: 0] write_byteenable;
  wire             write_chipselect;
  reg              write_got_endofpacket;
  wire             write_select;
  wire             write_write_n;
  wire    [ 31: 0] write_writedata;
  reg     [ 25: 0] writeaddress;
  wire    [  4: 0] writeaddress_inc;
  reg     [ 24: 0] writelength;
  reg              writelength_eq_0;
  assign clk_en = 1;
  dma_read_data_mux the_dma_read_data_mux
    (
      .byte               (byte),
      .clk                (clk),
      .clk_en             (clk_en),
      .dma_ctl_address    (dma_ctl_address),
      .dma_ctl_chipselect (dma_ctl_chipselect),
      .dma_ctl_write_n    (dma_ctl_write_n),
      .dma_ctl_writedata  (dma_ctl_writedata),
      .fifo_wr_data       (fifo_wr_data),
      .hw                 (hw),
      .read_readdata      (read_readdata),
      .read_readdatavalid (read_readdatavalid),
      .readaddress        (readaddress),
      .readaddress_inc    (readaddress_inc),
      .reset_n            (reset_n),
      .word               (word)
    );

  dma_byteenables the_dma_byteenables
    (
      .byte             (byte),
      .hw               (hw),
      .word             (word),
      .write_address    (write_address),
      .write_byteenable (write_byteenable)
    );

  assign dma_ctl_readyfordata = ~busy;