full_1c20.v

基于Nios II的汽车智能防盗导航系统核心作为嵌入式系统发展趋势

  //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //cpu_jtag_debug_module_address mux, which is an e_mux
  assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (cpu_data_master_address_to_slave >> 2) :
    (cpu_instruction_master_address_to_slave >> 2);

  //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
    end


  //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;

  //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_jtag_debug_module_counter = 0;
  //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

  // synthesis attribute cpu_jtag_debug_module_arbitrator auto_dissolve FALSE

endmodule


module cpu_custom_instruction_master_arbitrator (
                                                  // inputs:
                                                   bswap_cpu_s1_result_from_sa,
                                                   clk,
                                                   cpu_custom_instruction_master_combo_n,
                                                   custominstruction_cpu_s1_result_from_sa,
                                                   reset_n,

                                                  // outputs:
                                                   bswap_cpu_s1_select,
                                                   cpu_custom_instruction_master_combo_result,
                                                   cpu_custom_instruction_master_reset_n,
                                                   custominstruction_cpu_s1_select
                                                );

  output           bswap_cpu_s1_select;
  output  [ 31: 0] cpu_custom_instruction_master_combo_result;
  output           cpu_custom_instruction_master_reset_n;
  output           custominstruction_cpu_s1_select;
  input   [ 31: 0] bswap_cpu_s1_result_from_sa;
  input            clk;
  input   [  7: 0] cpu_custom_instruction_master_combo_n;
  input   [ 31: 0] custominstruction_cpu_s1_result_from_sa;
  input            reset_n;

  wire             bswap_cpu_s1_select;
  wire    [ 31: 0] cpu_custom_instruction_master_combo_result;
  wire             cpu_custom_instruction_master_reset_n;
  wire             custominstruction_cpu_s1_select;
  //cpu_custom_instruction_master_combo_result mux, which is an e_mux
  assign cpu_custom_instruction_master_combo_result = ({32 {bswap_cpu_s1_select}} & bswap_cpu_s1_result_from_sa) |
    ({32 {custominstruction_cpu_s1_select}} & custominstruction_cpu_s1_result_from_sa);

  //cpu_custom_instruction_master_reset_n local reset_n, which is an e_assign
  assign cpu_custom_instruction_master_reset_n = reset_n;

  assign custominstruction_cpu_s1_select = {cpu_custom_instruction_master_combo_n[0] } == 1'h1;
  assign bswap_cpu_s1_select = {cpu_custom_instruction_master_combo_n[0] } == 1'h0;

  // synthesis attribute cpu_custom_instruction_master_arbitrator auto_dissolve FALSE

endmodule


module cpu_data_master_arbitrator (
                                    // inputs:
                                     button_pio_s1_readdata_from_sa,
                                     clk,
                                     cpu_data_master_address,
                                     cpu_data_master_byteenable_ext_flash_s1,
                                     cpu_data_master_debugaccess,
                                     cpu_data_master_granted_DSR_pio_s1,
                                     cpu_data_master_granted_alarm_pio_s1,
                                     cpu_data_master_granted_button_pio_s1,
                                     cpu_data_master_granted_cpu_jtag_debug_module,
                                     cpu_data_master_granted_epcs_controller_epcs_control_port,
                                     cpu_data_master_granted_ext_flash_s1,
                                     cpu_data_master_granted_ext_ram_s1,
                                     cpu_data_master_granted_high_res_timer_s1,
                                     cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_granted_key_pio_s1,
                                     cpu_data_master_granted_lcd_ctrl_s1,
                                     cpu_data_master_granted_lcd_data_s1,
                                     cpu_data_master_granted_lcd_display_control_slave,
                                     cpu_data_master_granted_led_pio_s1,
                                     cpu_data_master_granted_reconfig_request_pio_s1,
                                     cpu_data_master_granted_sdram_s1,
                                     cpu_data_master_granted_seven_seg_pio_s1,
                                     cpu_data_master_granted_sys_clk_timer_s1,
                                     cpu_data_master_granted_sysid_control_slave,
                                     cpu_data_master_granted_uart1_s1,
                                     cpu_data_master_qualified_request_DSR_pio_s1,
                                     cpu_data_master_qualified_request_alarm_pio_s1,
                                     cpu_data_master_qualified_request_button_pio_s1,
                                     cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                     cpu_data_master_qualified_request_epcs_controller_epcs_control_port,
                                     cpu_data_master_qualified_request_ext_flash_s1,
                                     cpu_data_master_qualified_request_ext_ram_s1,
                                     cpu_data_master_qualified_request_high_res_timer_s1,
                                     cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_qualified_request_key_pio_s1,
                                     cpu_data_master_qualified_request_lcd_ctrl_s1,
                                     cpu_data_master_qualified_request_lcd_data_s1,
                                     cpu_data_master_qualified_request_lcd_display_control_slave,
                                     cpu_data_master_qualified_request_led_pio_s1,
                                     cpu_data_master_qualified_request_reconfig_request_pio_s1,
                                     cpu_data_master_qualified_request_sdram_s1,
                                     cpu_data_master_qualified_request_seven_seg_pio_s1,
                                     cpu_data_master_qualified_request_sys_clk_timer_s1,
                                     cpu_data_master_qualified_request_sysid_control_slave,
                                     cpu_data_master_qualified_request_uart1_s1,
                                     cpu_data_master_read,
                                     cpu_data_master_read_data_valid_DSR_pio_s1,
                                     cpu_data_master_read_data_valid_alarm_pio_s1,
                                     cpu_data_master_read_data_valid_button_pio_s1,
                                     cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                     cpu_data_master_read_data_valid_epcs_controller_epcs_control_port,
                                     cpu_data_master_read_data_valid_ext_flash_s1,
                                     cpu_data_master_read_data_valid_ext_ram_s1,
                                     cpu_data_master_read_data_valid_high_res_timer_s1,
                                     cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_read_data_valid_key_pio_s1,
                                     cpu_data_master_read_data_valid_lcd_ctrl_s1,
                                     cpu_data_master_read_data_valid_lcd_data_s1,
                                     cpu_data_master_read_data_valid_lcd_display_control_slave,
                                     cpu_data_master_read_data_valid_led_pio_s1,
                                     cpu_data_master_read_data_valid_reconfig_request_pio_s1,
                                     cpu_data_master_read_data_valid_sdram_s1,
                                     cpu_data_master_read_data_valid_sdram_s1_shift_register,
                                     cpu_data_master_read_data_valid_seven_seg_pio_s1,
                                     cpu_data_master_read_data_valid_sys_clk_timer_s1,
                                     cpu_data_master_read_data_valid_sysid_control_slave,
                                     cpu_data_master_read_data_valid_uart1_s1,
                                     cpu_data_master_requests_DSR_pio_s1,
                                     cpu_data_master_requests_alarm_pio_s1,
                                     cpu_data_master_requests_button_pio_s1,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_epcs_controller_epcs_control_port,
                                     cpu_data_master_requests_ext_flash_s1,
                                     cpu_data_master_requests_ext_ram_s1,
                                     cpu_data_master_requests_high_res_timer_s1,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_key_pio_s1,
                                     cpu_data_master_requests_lcd_ctrl_s1,
                                     cpu_data_master_requests_lcd_data_s1,
                                     cpu_data_master_requests_lcd_display_control_slave,
                                     cpu_data_master_requests_led_pio_s1,
                                     cpu_data_master_requests_reconfig_request_pio_s1,
                                     cpu_data_master_requests_sdram_s1,
                                     cpu_data_master_requests_seven_seg_pio_s1,
                                     cpu_data_master_requests_sys_clk_timer_s1,
                                     cpu_data_master_requests_sysid_control_slave,
                                     cpu_data_master_requests_uart1_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_DSR_pio_s1_end_xfer,
                                     d1_alarm_pio_s1_end_xfer,
                                     d1_button_pio_s1_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_epcs_controller_epcs_control_port_end_xfer,
                                     d1_ext_ram_bus_avalon_slave_end_xfer,
                                     d1_high_res_timer_s1_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_key_pio_s1_end_xfer,
                                     d1_lcd_ctrl_s1_end_xfer,
                                     d1_lcd_data_s1_end_xfer,
                                     d1_lcd_display_control_slave_end_xfer,
                                     d1_led_pio_s1_end_xfer,
                                     d1_reconfig_request_pio_s1_end_xfer,
                                     d1_sdram_s1_end_xfer,
                                     d1_seven_seg_pio_s1_end_xfer,
                                     d1_sys_clk_timer_s1_end_xfer,
                                     d1_sysid_control_slave_end_xfer,
                                     d1_uart1_s1_end_xfer,
                                     epcs_controller_epcs_control_port_irq_from_sa,
                                     epcs_controller_epcs_control_port_readdata_from_sa,
                                     ext_flash_s1_wait_counter_eq_0,
                                     ext_flash_s1_wait_c