📄 button_pio.v
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//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related net list (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only to
//program PLD devices (but not masked PLD devices) from Altera. Any other
//use of such megafunction design, net list, support information, device
//programming or simulation file, or any other related documentation or
//information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to
//the intellectual property, including patents, copyrights, trademarks,
//trade secrets, or maskworks, embodied in any such megafunction design,
//net list, support information, device programming or simulation file, or
//any other related documentation or information provided by Altera or a
//megafunction partner, remains with Altera, the megafunction partner, or
//their respective licensors. No other licenses, including any licenses
//needed under any third party's intellectual property, are provided herein.
//Copying or modifying any file, or portion thereof, to which this notice
//is attached violates this copyright.
// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module button_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [ 3: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 3: 0] readdata;
assign clk_en = 1;
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
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