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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning music.vhd
Scanning music.vhd
Writing music.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/music/music.vhd in Library work.Entity <music> (Architecture <behave>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <music> (Architecture <behave>).Entity <music> analyzed. Unit <music> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <music>. Related source file is D:/music/music.vhd. Found 16x11-bit ROM for signal <tone>. Found 128x4-bit ROM for signal <$n0023>. Found 1-bit register for signal <spk>. Found 5-bit comparator less for signal <$n0022> created at line 31. Found 12-bit comparator greatequal for signal <$n0288> created at line 393. Found 1-bit register for signal <clk>. Found 1-bit register for signal <clk10>. Found 18-bit up counter for signal <clk10_count>. Found 5-bit up counter for signal <cnt1>. Found 8-bit up counter for signal <time1>. Found 8-bit up counter for signal <time2>. Found 11-bit up counter for signal <tone_count>. Found 4-bit register for signal <tone_index>. Found 1 1-bit 2-to-1 multiplexers. Summary: inferred 2 ROM(s). inferred 5 Counter(s). inferred 3 D-type flip-flop(s). inferred 2 Comparator(s).Unit <music> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 2 16x11-bit ROM : 1 128x4-bit ROM : 1# Registers : 4 1-bit register : 3 4-bit register : 1# Counters : 5 5-bit up counter : 1 18-bit up counter : 1 8-bit up counter : 2 11-bit up counter : 1# Multiplexers : 1 2-to-1 multiplexer : 1# Comparators : 2 5-bit comparator less : 1 12-bit comparator greatequal : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <music> ... implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : time2_1 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : time1_4 implementation constraint: INIT=r : time2_4 implementation constraint: INIT=r : tone_index_1 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : time1_3 implementation constraint: INIT=r : tone_index_3 implementation constraint: INIT=r : tone_index_2 implementation constraint: INIT=r : tone_index_0 implementation constraint: INIT=r : time2_0 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : time2_2 implementation constraint: INIT=r : time2_3 implementation constraint: INIT=r : time1_5 implementation constraint: INIT=r : time1_7 implementation constraint: INIT=r : time1_6 implementation constraint: INIT=r : time1_0 implementation constraint: INIT=r : time1_1 implementation constraint: INIT=r : time1_2 implementation constraint: INIT=r : time2_5 implementation constraint: INIT=r : time2_7 implementation constraint: INIT=r : time2_6Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500 music.ngc music.ngd Reading NGO file "D:/music/music.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "music.ngd" ...Writing NGDBUILD log file "music.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/music/music.vhd in Library work.Architecture behave of Entity music is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <music> (Architecture <behave>).Entity <music> analyzed. Unit <music> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <music>. Related source file is D:/music/music.vhd. Found 16x11-bit ROM for signal <tone>. Found 128x4-bit ROM for signal <$n0023>. Found 1-bit register for signal <spk>. Found 5-bit comparator less for signal <$n0022> created at line 31. Found 12-bit comparator greatequal for signal <$n0288> created at line 393. Found 1-bit register for signal <clk>. Found 1-bit register for signal <clk10>. Found 18-bit up counter for signal <clk10_count>. Found 5-bit up counter for signal <cnt1>. Found 8-bit up counter for signal <time1>. Found 8-bit up counter for signal <time2>. Found 11-bit up counter for signal <tone_count>. Found 4-bit register for signal <tone_index>. Found 1 1-bit 2-to-1 multiplexers. Summary: inferred 2 ROM(s). inferred 5 Counter(s). inferred 3 D-type flip-flop(s). inferred 2 Comparator(s).Unit <music> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 2 16x11-bit ROM : 1 128x4-bit ROM : 1# Registers : 4 1-bit register : 3 4-bit register : 1# Counters : 5 5-bit up counter : 1 18-bit up counter : 1 8-bit up counter : 2 11-bit up counter : 1# Multiplexers : 1 2-to-1 multiplexer : 1# Comparators : 2 5-bit comparator less : 1 12-bit comparator greatequal : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Library "C:/Xilinx/xc9500/data/lib.xst" ConsultedLibrary "C:/Xilinx/data/librtl.xst" ConsultedOptimizing unit <music> ... implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : time2_1 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : time1_4 implementation constraint: INIT=r : time2_4 implementation constraint: INIT=r : tone_index_1 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : time1_3 implementation constraint: INIT=r : tone_index_3 implementation constraint: INIT=r : tone_index_2 implementation constraint: INIT=r : tone_index_0 implementation constraint: INIT=r : time2_0 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : time2_2 implementation constraint: INIT=r : time2_3 implementation constraint: INIT=r : time1_5 implementation constraint: INIT=r : time1_7 implementation constraint: INIT=r : time1_6 implementation constraint: INIT=r : time1_0 implementation constraint: INIT=r : time1_1 implementation constraint: INIT=r : time1_2 implementation constraint: INIT=r : time2_5 implementation constraint: INIT=r : time2_7 implementation constraint: INIT=r : time2_6Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 5.2i - ngdbuild F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500 music.ngc music.ngd Reading NGO file "D:/music/music.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "music.ngd" ...Writing NGDBUILD log file "music.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2i - CPLD Optimizer/Partitioner F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95108-PC84.Flattening design..Multi-level logic optimization...Timing optimization.............................................................................................................Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 68 equations into 6 function blocks...........................Design music has been optimized and fit into device XC95108-7-PC84.Completed process "Fit".Started process "Generate Timing".Release 5.2i - Timing Report Generator F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Path tracing .........The number of paths traced: 871.Generating performance summary ...Generating Pad-to-Pad delay section ...Generating Clock-to-Output-Pad delay section ...Generating Setup-To-Clock-At-Pad delay section ...Generating Register-To-Register delay section ... Cycle time table for clock inclk ... Cycle time table for clock clk.Q ... Cycle time table for clock clk10.Q ...music.tim has been created.Generating Stamp model files music.mod, music.data ...music.mod has been created.music.data has been created.Completed process "Generate Timing".
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Started process "Generate Post-Fit Simulation Model".Release 5.2i - Timing Simulation Interface F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Creating NGA for simulation.
Release 5.2i - ngd2vhdl F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.ngd2vhdl: Reading design music.nga ...WARNING:NetListWriters:431 - Design does not contain hierarchical blocks with KEEP_HIERARCHY property. Hierarchy will not be retained.ngd2vhdl: Flattening design ...ngd2vhdl: Flattening design completed.ngd2vhdl: Specializing design ...ngd2vhdl: Specializing design completed.ngd2vhdl: Processing design ...ngd2vhdl: Preping physical only global signals ...ngd2vhdl: Preping design's networks ...ngd2vhdl: Preping design's macros ...ngd2vhdl: Preping design completed.ngd2vhdl: Writing VHDL netlist music_timesim.vhd ...ngd2vhdl: Setting external property filter file to C:/Xilinx/data/xdm2vhdl.prp.ngd2vhdl: Completed writing file music_timesim.vhd.ngd2vhdl: Writing VHDL SDF file music_timesim.sdf ...ngd2vhdl: Completed writing file music_timesim.sdf.ngd2vhdl: Total memory usage is 35032 kilobytesCreated music_timesim.vhdCompleted process "Generate Post-Fit Simulation Model".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Post-Fit Simulation Model".Release 5.2i - ngd2vhdl F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.ngd2vhdl: Reading design music.nga ...WARNING:NetListWriters:431 - Design does not contain hierarchical blocks with KEEP_HIERARCHY property. Hierarchy will not be retained.ngd2vhdl: Flattening design ...ngd2vhdl: Flattening design completed.ngd2vhdl: Specializing design ...ngd2vhdl: Specializing design completed.ngd2vhdl: Processing design ...ngd2vhdl: Preping physical only global signals ...ngd2vhdl: Preping design's networks ...ngd2vhdl: Preping design's macros ...ngd2vhdl: Preping design completed.ngd2vhdl: Writing VHDL netlist music_timesim.vhd ...ngd2vhdl: Setting external property filter file to C:/Xilinx/data/xdm2vhdl.prp.ngd2vhdl: Completed writing file music_timesim.vhd.ngd2vhdl: Writing VHDL SDF file music_timesim.sdf ...ngd2vhdl: Completed writing file music_timesim.sdf.ngd2vhdl: Total memory usage is 35032 kilobytesCreated music_timesim.vhdCompleted process "Generate Post-Fit Simulation Model".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate IBIS Model".IBISWRITER: Xilinx IBIS File Writer F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Mon Apr 20 11:19:01 2009Xilinx IBISWriter has successfully completedCompleted process "Generate IBIS Model".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file D:/music/music.vhd in Library work.Entity <music> (Architecture <behave>) compiled.tdtfi(vhdl) completed successfully.
Release 5.2i - spl2sym F.28Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.⌨️ 快捷键说明
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