music.rpt

用CPLD做音乐发生器

time2<1>             ..XXX.XXXXXXXXX......................... 12      12
tone_index<3>        ..XXX.XXXXXXXX.......................... 11      11
BUF_tone_index<2>    XX.XXXXXXXXXXX.......................... 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining:               13/23
Number of signals used by logic mapping into function block:  13
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB6_1               (b)     
(unused)              0       0     0   5     FB6_2         45    I/O     
(unused)              0       0     0   5     FB6_3         46    I/O     
(unused)              0       0     0   5     FB6_4               (b)     
(unused)              0       0     0   5     FB6_5         47    I/O     
(unused)              0       0     0   5     FB6_6         48    I/O     
(unused)              0       0     0   5     FB6_7               (b)     
(unused)              0       0     0   5     FB6_8         50    I/O     
(unused)              0       0     0   5     FB6_9         51    I/O     
(unused)              0       0     0   5     FB6_10              (b)     
time2<7>/time2<7>_SETF__$INT
                      1       0     0   4     FB6_11  STD   52    I/O     (b)
time1<7>/time1<7>_SETF__$INT
                      1       0     0   4     FB6_12  STD   53    I/O     (b)
$OpTx$$OpTx$FX_DC$51_INV$560
                      1       0     0   4     FB6_13  STD         (b)     (b)
$OpTx$$OpTx$FX_DC$48_INV$559
                      1       0     0   4     FB6_14  STD   54    I/O     (b)
$OpTx$$OpTx$FX_DC$47_INV$558
                      1       0     0   4     FB6_15  STD   55    I/O     (b)
$OpTx$$OpTx$FX_DC$80_INV$562
                      2       0     0   3     FB6_16  STD         (b)     (b)
$OpTx$$OpTx$FX_DC$73_INV$561
                      2       0     0   3     FB6_17  STD   56    I/O     (b)
$OpTx$FX_DC$83        3       0     0   2     FB6_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: enable1            6: time1<3>          10: time2<1> 
  2: enable2            7: time1<5>          11: time2<2> 
  3: time1<0>           8: time1<6>          12: time2<3> 
  4: time1<1>           9: time2<0>          13: time2<4> 
  5: time1<2>         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
time2<7>/time2<7>_SETF__$INT 
                     XX...................................... 2       2
time1<7>/time1<7>_SETF__$INT 
                     XX...................................... 2       2
$OpTx$$OpTx$FX_DC$51_INV$560 
                     .........XX............................. 2       2
$OpTx$$OpTx$FX_DC$48_INV$559 
                     ........X.X............................. 2       2
$OpTx$$OpTx$FX_DC$47_INV$558 
                     ........X.X............................. 2       2
$OpTx$$OpTx$FX_DC$80_INV$562 
                     ..XX.XXX................................ 5       5
$OpTx$$OpTx$FX_DC$73_INV$561 
                     .........X.XX........................... 3       3
$OpTx$FX_DC$83       ....XXXX................................ 4       4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.

$OpTx$$OpTx$FX_DC$47_INV$558 = !(time2<0>) & time2<2>;    

$OpTx$$OpTx$FX_DC$48_INV$559 = time2<0> & !(time2<2>);    

$OpTx$$OpTx$FX_DC$51_INV$560 = time2<2> & time2<1>;    

$OpTx$$OpTx$FX_DC$73_INV$561 = time2<4> & time2<3>
	# !(time2<1>) & !(time2<4>) & !(time2<3>);    

$OpTx$$OpTx$FX_DC$80_INV$562 = !(time1<3>) & time1<5> & !(time1<6>)
	# !(time1<3>) & time1<0> & !(time1<5>) & time1<1>;    

$OpTx$FX_DC$72 = ;Imported pterms FB5_2
	  time2<4>.FBK.LFBK & !(time2<6>.FBK.LFBK)
	# !(time2<1>.FBK.LFBK) & !(time2<4>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK);    

$OpTx$FX_DC$79 = time2<2>.FBK.LFBK & !(time2<1>.FBK.LFBK) & 
	time2<4>.FBK.LFBK & !(time2<3>.FBK.LFBK)
;Imported pterms FB5_6
	# time2<0>.FBK.LFBK & !(time2<2>.FBK.LFBK) & 
	time2<1>.FBK.LFBK & time2<3>.FBK.LFBK;    

$OpTx$FX_DC$83 = time1<3> & time1<5> & !(time1<6>)
	# !(time1<3>) & time1<2> & time1<5>
	# !(time1<3>) & !(time1<5>) & time1<6>;    

BUF_tone_index<2> = enable1 & !(enable2) & !(time1<7>) & $OpTx$FX_DC$83
	# !(enable1) & enable2 & $OpTx$$OpTx$FX_DC$47_INV$558 & 
	!(time2<6>.FBK.LFBK) & time2<5>.FBK.LFBK & !(time2<3>.FBK.LFBK) & 
	!(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	!(time2<1>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & !(time2<3>.FBK.LFBK) & 
	!(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	time2<6>.FBK.LFBK & !(time2<5>.FBK.LFBK) & time2<3>.FBK.LFBK & 
	!(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<2>.FBK.LFBK) & 
	!(time2<6>.FBK.LFBK) & time2<5>.FBK.LFBK & time2<3>.FBK.LFBK & 
	!(time2<7>.FBK.LFBK)
;Imported pterms FB5_16
	# !(enable1) & enable2 & $OpTx$$OpTx$FX_DC$47_INV$558 & 
	!(time2<4>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & !(time2<5>.FBK.LFBK) & 
	!(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	!(time2<4>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & !(time2<5>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<0>.FBK.LFBK) & 
	!(time2<1>.FBK.LFBK) & time2<4>.FBK.LFBK & !(time2<5>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	!(time2<1>.FBK.LFBK) & !(time2<4>.FBK.LFBK) & !(time2<5>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<1>.FBK.LFBK) & 
	time2<4>.FBK.LFBK & time2<6>.FBK.LFBK & !(time2<5>.FBK.LFBK) & 
	time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
;Imported pterms FB5_15
	# !(enable1) & enable2 & !($OpTx$$OpTx$FX_DC$47_INV$558) & 
	time2<4>.FBK.LFBK & !(time2<6>.FBK.LFBK) & !(time2<5>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	!(time2<4>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & !(time2<5>.FBK.LFBK) & 
	!(time2<3>.FBK.LFBK) & time2<7>.FBK.LFBK
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	time2<1>.FBK.LFBK & !(time2<4>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & 
	!(time2<5>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<2>.FBK.LFBK) & 
	!(time2<1>.FBK.LFBK) & !(time2<4>.FBK.LFBK) & !(time2<6>.FBK.LFBK) & 
	!(time2<5>.FBK.LFBK) & time2<7>.FBK.LFBK
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	time2<2>.FBK.LFBK & !(time2<1>.FBK.LFBK) & time2<4>.FBK.LFBK & 
	time2<5>.FBK.LFBK & time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
;Imported pterms FB5_18
	# !(enable1) & enable2 & $OpTx$$OpTx$FX_DC$47_INV$558 & 
	time2<1>.FBK.LFBK & time2<4>.FBK.LFBK & time2<6>.FBK.LFBK & 
	time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<0>.FBK.LFBK) & 
	!(time2<4>.FBK.LFBK) & time2<6>.FBK.LFBK & !(time2<5>.FBK.LFBK) & 
	time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<2>.FBK.LFBK & 
	time2<1>.FBK.LFBK & time2<4>.FBK.LFBK & time2<6>.FBK.LFBK & 
	!(time2<5>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<2>.FBK.LFBK) & 
	!(time2<1>.FBK.LFBK) & !(time2<4>.FBK.LFBK) & time2<6>.FBK.LFBK & 
	time2<5>.FBK.LFBK & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<1>.FBK.LFBK) & 
	time2<4>.FBK.LFBK & !(time2<6>.FBK.LFBK) & time2<5>.FBK.LFBK & 
	time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
;Imported pterms FB5_1
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	time2<2>.FBK.LFBK & time2<1>.FBK.LFBK & !(time2<4>.FBK.LFBK) & 
	time2<5>.FBK.LFBK & !(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	!(time2<2>.FBK.LFBK) & time2<1>.FBK.LFBK & time2<4>.FBK.LFBK & 
	time2<6>.FBK.LFBK & time2<3>.FBK.LFBK & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	!(time2<2>.FBK.LFBK) & time2<1>.FBK.LFBK & !(time2<4>.FBK.LFBK) & 
	time2<6>.FBK.LFBK & !(time2<5>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & time2<0>.FBK.LFBK & 
	!(time2<2>.FBK.LFBK) & !(time2<1>.FBK.LFBK) & time2<6>.FBK.LFBK & 
	time2<5>.FBK.LFBK & !(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK)
	# !(enable1) & enable2 & !(time2<0>.FBK.LFBK) & 
	!(time2<2>.FBK.LFBK) & time2<1>.FBK.LFBK & time2<6>.FBK.LFBK & 
	time2<5>.FBK.LFBK & !(time2<3>.FBK.LFBK) & !(time2<7>.FBK.LFBK);    

clk.D = !(cnt1<1>.FBK.LFBK) & !(cnt1<4>.FBK.LFBK)
	# !(cnt1<4>.FBK.LFBK) & !(cnt1<2>.FBK.LFBK)
	# !(cnt1<4>.FBK.LFBK) & !(cnt1<3>.FBK.LFBK)
	# !(cnt1<4>.FBK.LFBK) & !(cnt1<0>.FBK.LFBK)
	# cnt1<1>.FBK.LFBK & cnt1<2>.FBK.LFBK & 
	cnt1<3>.FBK.LFBK & !(cnt1<0>.FBK.LFBK) & clk.FBK.LFBK;
   clk.CLK = inclk;	// GCK    

clk10.T = clk10_count<0> & !(clk10_count<14>) & 
	!(clk10_count<15>) & clk10_count<1>.FBK.LFBK & clk10_count<2>.FBK.LFBK & 
	clk10_count<3>.FBK.LFBK & clk10_count<4>.FBK.LFBK & clk10_count<5>.FBK.LFBK & 
	clk10_count<6>.FBK.LFBK & clk10_count<7>.FBK.LFBK & clk10_count<8>.FBK.LFBK & 
	clk10_count<9>.FBK.LFBK & clk10_count<10>.FBK.LFBK & 
	clk10_count<11>.FBK.LFBK & clk10_count<12>.FBK.LFBK & 
	clk10_count<13>.FBK.LFBK & !(clk10_count<16>.FBK.LFBK) & 
	!(clk10_count<17>.FBK.LFBK);
   clk10.CLK = clk;    

clk10_count<0>.T = Vcc;
   clk10_count<0>.CLK = clk.FBK.LFBK;    

clk10_count<10>.T = clk10_count<0> & clk10_count<1>.FBK.LFBK & 
	clk10_count<2>.FBK.LFBK & clk10_count<3>.FBK.LFBK & clk10_count<4>.FBK.LFBK & 
	clk10_count<5>.FBK.LFBK & clk10_count<6>.FBK.LFBK & clk10_count<7>.FBK.LFBK & 
	clk10_count<8>.FBK.LFBK & clk10_count<9>.FBK.LFBK;
   clk10_count<10>.CLK = clk;    

clk10_count<11>.T = clk10_count<0> & clk10_count<1>.FBK.LFBK & 
	clk10_count<2>.FBK.LFBK & clk10_count<3>.FBK.LFBK & clk10_count<4>.FBK.LFBK & 
	clk10_count<5>.FBK.LFBK & clk10_count<6>.FBK.LFBK & clk10_count<7>.FBK.LFBK & 
	clk10_count<8>.FBK.LFBK & clk10_count<9>.FBK.LFBK & 
	clk10_count<10>.FBK.LFBK;
   clk10_count<11>.CLK = clk;    

clk10_count<12>.T = clk10_count<0> & clk10_count<1>.FBK.LFBK &