📄 music.rpt
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cpldfit: version F.28 Xilinx Inc.
Fitter Report
Design Name: music Date: 4-20-2009, 4:06PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
68 /108 ( 63%) 351 /540 ( 65%) 57 /108 ( 53%) 4 /69 ( 6%) 139/216 ( 64%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 3 60
Output : 1 1 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 4 4
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 57
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'inclk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 68 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 68 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
$OpTx$$OpTx$FX_DC$47_INV$558 1 2 FB6_15 STD 55 I/O (b)
$OpTx$$OpTx$FX_DC$48_INV$559 1 2 FB6_14 STD 54 I/O (b)
$OpTx$$OpTx$FX_DC$51_INV$560 1 2 FB6_13 STD (b) (b)
$OpTx$$OpTx$FX_DC$73_INV$561 2 3 FB6_17 STD 56 I/O (b)
$OpTx$$OpTx$FX_DC$80_INV$562 2 5 FB6_16 STD (b) (b)
$OpTx$FX_DC$72 2 4 FB5_1 STD (b) (b)
$OpTx$FX_DC$79 2 5 FB5_7 STD (b) (b)
$OpTx$FX_DC$83 3 4 FB6_18 STD (b) (b)
BUF_tone_index<2> 25 13 FB5_17 STD 44 I/O (b)
clk 5 6 FB4_18 STD (b) (b) RESET
clk10 2 19 FB2_18 STD (b) (b) RESET
clk10_count<0> 1 1 FB4_4 STD (b) (b) RESET
clk10_count<10> 2 11 FB2_17 STD 84 I/O (b) RESET
clk10_count<11> 2 12 FB2_16 STD 83 I/O (b) RESET
clk10_count<12> 2 13 FB2_15 STD 82 I/O (b) RESET
clk10_count<13> 2 14 FB2_14 STD 81 I/O (b) RESET
clk10_count<14> 2 15 FB3_16 STD 26 I/O (b) RESET
clk10_count<15> 2 16 FB3_18 STD (b) (b) RESET
clk10_count<16> 2 17 FB2_13 STD (b) (b) RESET
clk10_count<17> 2 18 FB2_12 STD 80 I/O (b) RESET
clk10_count<1> 2 2 FB2_11 STD 79 I/O (b) RESET
clk10_count<2> 2 3 FB2_10 STD (b) (b) RESET
clk10_count<3> 2 4 FB2_9 STD 77 GTS/I/O (b) RESET
clk10_count<4> 2 5 FB2_8 STD 76 GTS/I/O (b) RESET
clk10_count<5> 2 6 FB2_7 STD (b) (b) RESET
clk10_count<6> 2 7 FB2_6 STD 75 I/O (b) RESET
clk10_count<7> 2 8 FB2_5 STD 74 GSR/I/O (b) RESET
clk10_count<8> 2 9 FB2_4 STD (b) (b) RESET
clk10_count<9> 2 10 FB2_3 STD 72 I/O (b) RESET
cnt1<0> 1 5 FB4_3 STD 58 I/O (b) RESET
cnt1<1> 2 5 FB4_8 STD 63 I/O (b) RESET
cnt1<2> 2 5 FB4_7 STD (b) (b) RESET
cnt1<3> 2 5 FB4_6 STD 62 I/O (b) RESET
cnt1<4> 2 5 FB4_5 STD 61 I/O (b) RESET
spk 7 17 FB3_8 STD FAST 19 I/O O RESET
time1<0> 3 10 FB1_2 STD 1 I/O (b) RESET
time1<1> 4 10 FB4_17 STD 70 I/O (b) RESET
time1<2> 4 10 FB4_16 STD (b) (b) RESET
time1<3> 3 5 FB4_11 STD 66 I/O (b) RESET
time1<4> 4 10 FB4_15 STD 69 I/O (b) RESET
time1<5> 3 7 FB4_10 STD (b) (b) RESET
time1<6> 3 8 FB4_9 STD 65 I/O (b) RESET
time1<7> 4 10 FB4_14 STD 68 I/O (b) RESET
time1<7>/time1<7>_SETF__$INT 1 2 FB6_12 STD 53 I/O (b)
time2<0> 4 12 FB5_5 STD 34 I/O (b) RESET
time2<1> 6 12 FB5_10 STD (b) (b) RESET
time2<2> 6 12 FB5_9 STD 37 I/O (b) RESET
time2<3> 4 7 FB5_4 STD (b) (b) RESET
time2<4> 6 12 FB5_8 STD 36 I/O (b) RESET
time2<5> 4 9 FB5_3 STD 33 I/O (b) RESET
time2<6> 4 10 FB5_2 STD 32 I/O (b) RESET
time2<7> 6 12 FB5_6 STD 35 I/O (b) RESET
time2<7>/time2<7>_SETF__$INT 1 2 FB6_11 STD 52 I/O (b)
tone_count<0> 4 16 FB4_13 STD (b) (b) RESET
tone_count<10> 4 16 FB4_12 STD 67 I/O (b) RESET
tone_count<1> 5 16 FB3_15 STD 25 I/O (b) RESET
tone_count<2> 8 16 FB3_12 STD 23 I/O (b) RESET
tone_count<3> 9 16 FB3_17 STD 31 I/O (b) RESET
tone_count<4> 10 16 FB3_2 STD 14 I/O (b) RESET
tone_count<5> 10 16 FB3_4 STD (b) (b) RESET
tone_count<6> 10 16 FB3_6 STD 18 I/O I RESET
tone_count<7> 9 16 FB3_9 STD 20 I/O (b) RESET
tone_count<8> 9 16 FB3_10 STD (b) (b) RESET
tone_count<9> 7 16 FB3_13 STD (b) (b) RESET
tone_index<0> 26 24 FB1_17 STD 13 I/O (b) RESET
tone_index<1> 26 18 FB1_6 STD 4 I/O (b) RESET
tone_index<2> 26 14 FB1_11 STD 7 I/O (b) RESET
tone_index<3> 21 11 FB5_12 STD 40 I/O (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
enable1 FB3_5 17 I/O I
enable2 FB3_6 18 I/O I
inclk FB1_12 9 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 4 29 29 81 0/0 12
FB2 16 19 19 32 0/0 12
FB3 12 32 32 88 1/0 12
FB4 16 31 31 48 0/0 11
FB5 12 15 15 90 0/0 11
FB6 8 13 13 12 0/0 11
---- ----- ----- -----
68 351 1/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\5 0 FB1_1 (b) (b)
time1<0> 3 0 /\1 1 FB1_2 STD 1 I/O (b)
(unused) 0 0 \/1 4 FB1_3 2 I/O (b)
(unused) 0 0 \/5 0 FB1_4 (b) (b)
(unused) 0 0 \/5 0 FB1_5 3 I/O (b)
tone_index<1> 26 21<- 0 0 FB1_6 STD 4 I/O (b)
(unused) 0 0 /\5 0 FB1_7 (b) (b)
(unused) 0 0 /\5 0 FB1_8 5 I/O (b)
(unused) 0 0 \/5 0 FB1_9 6 I/O (b)
(unused) 0 0 \/5 0 FB1_10 (b) (b)
tone_index<2> 26 21<- 0 0 FB1_11 STD 7 I/O (b)
(unused) 0 0 /\5 0 FB1_12 9 GCK/I/O GCK
(unused) 0 0 /\5 0 FB1_13 (b) (b)
(unused) 0 0 /\1 4 FB1_14 10 GCK/I/O (b)
(unused) 0 0 \/5 0 FB1_15 11 I/O (b)
(unused) 0 0 \/5 0 FB1_16 12 GCK/I/O (b)
tone_index<0> 26 21<- 0 0 FB1_17 STD 13 I/O (b)
(unused) 0 0 /\5 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$47_INV$558
11: enable1 21: time1<7>/time1<7>_SETF__$INT
2: $OpTx$$OpTx$FX_DC$48_INV$559
12: enable2 22: time2<0>
3: $OpTx$$OpTx$FX_DC$51_INV$560
13: time1<0>.FBK.LFBK 23: time2<1>
4: $OpTx$$OpTx$FX_DC$73_INV$561
14: time1<1> 24: time2<2>
5: $OpTx$$OpTx$FX_DC$80_INV$562
15: time1<2> 25: time2<3>
6: $OpTx$FX_DC$72 16: time1<3> 26: time2<4>
7: $OpTx$FX_DC$79 17: time1<4> 27: time2<5>
8: $OpTx$FX_DC$83 18: time1<5> 28: time2<6>
9: BUF_tone_index<2> 19: time1<6> 29: time2<7>
10: clk10 20: time1<7>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
time1<0> .........X..XXXXXXXXX................... 10 10
tone_index<1> .........XXXXXXX.XXX.XXXXXXXX........... 18 18
tone_index<2> X......X.XXX.......X.XXXXXXXX........... 14 14
tone_index<0> .XXXXXX.XXXX..XXXXXX.XXXXXXXX........... 24 24
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 19/17
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
clk10_count<9> 2 0 0 3 FB2_3 STD 72 I/O (b)
clk10_count<8> 2 0 0 3 FB2_4 STD (b) (b)
clk10_count<7> 2 0 0 3 FB2_5 STD 74 GSR/I/O (b)
clk10_count<6> 2 0 0 3 FB2_6 STD 75 I/O (b)
clk10_count<5> 2 0 0 3 FB2_7 STD (b) (b)
clk10_count<4> 2 0 0 3 FB2_8 STD 76 GTS/I/O (b)
clk10_count<3> 2 0 0 3 FB2_9 STD 77 GTS/I/O (b)
clk10_count<2> 2 0 0 3 FB2_10 STD (b) (b)
clk10_count<1> 2 0 0 3 FB2_11 STD 79 I/O (b)
clk10_count<17> 2 0 0 3 FB2_12 STD 80 I/O (b)
clk10_count<16> 2 0 0 3 FB2_13 STD (b) (b)
clk10_count<13> 2 0 0 3 FB2_14 STD 81 I/O (b)
clk10_count<12> 2 0 0 3 FB2_15 STD 82 I/O (b)
clk10_count<11> 2 0 0 3 FB2_16 STD 83 I/O (b)
clk10_count<10> 2 0 0 3 FB2_17 STD 84 I/O (b)
clk10 2 0 0 3 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: clk 8: clk10_count<15> 14: clk10_count<4>.FBK.LFBK
2: clk10_count<0> 9: clk10_count<16>.FBK.LFBK
15: clk10_count<5>.FBK.LFBK
3: clk10_count<10>.FBK.LFBK
10: clk10_count<17>.FBK.LFBK
16: clk10_count<6>.FBK.LFBK
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