music_timesim.vhd

用CPLD做音乐发生器

  signal EXP12_EXP : STD_LOGIC; 
  signal tone_index_0_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_UIM : STD_LOGIC; 
  signal tone_index_0_D2_PT_2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_UIM : STD_LOGIC; 
  signal tone_index_0_D2_PT_3 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_UIM : STD_LOGIC; 
  signal tone_index_0_D2_PT_4 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_UIM : STD_LOGIC; 
  signal tone_index_0_D2_PT_5 : STD_LOGIC; 
  signal tone_index_0_D2 : STD_LOGIC; 
  signal EXP10_EXP : STD_LOGIC; 
  signal EXP11_EXP_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_UIM : STD_LOGIC; 
  signal EXP11_EXP_PT_1 : STD_LOGIC; 
  signal EXP11_EXP_PT_2 : STD_LOGIC; 
  signal EXP11_EXP_PT_3 : STD_LOGIC; 
  signal EXP11_EXP_PT_4 : STD_LOGIC; 
  signal EXP11_EXP_PT_5 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_UIM : STD_LOGIC; 
  signal EXP10_EXP_PT_0 : STD_LOGIC; 
  signal EXP10_EXP_PT_1 : STD_LOGIC; 
  signal EXP10_EXP_PT_2 : STD_LOGIC; 
  signal EXP10_EXP_PT_3 : STD_LOGIC; 
  signal EXP10_EXP_PT_4 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_Q : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_D : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_D1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_54_INV_1002_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_61_D2 : STD_LOGIC; 
  signal EXP0_EXP : STD_LOGIC; 
  signal EXP12_EXP_PT_0 : STD_LOGIC; 
  signal EXP12_EXP_PT_1 : STD_LOGIC; 
  signal EXP12_EXP_PT_2 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_UIM : STD_LOGIC; 
  signal EXP12_EXP_PT_3 : STD_LOGIC; 
  signal EXP12_EXP_PT_4 : STD_LOGIC; 
  signal EXP12_EXP_PT_5 : STD_LOGIC; 
  signal EXP0_EXP_PT_0 : STD_LOGIC; 
  signal EXP0_EXP_PT_1 : STD_LOGIC; 
  signal EXP0_EXP_PT_2 : STD_LOGIC; 
  signal EXP0_EXP_PT_3 : STD_LOGIC; 
  signal EXP0_EXP_PT_4 : STD_LOGIC; 
  signal EXP0_EXP_PT_5 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_Q : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_D : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_D1 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_OpTx_FX_DC_45_INV_1001_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_3 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_4 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2_PT_5 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_120_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_71_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_70_D2 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_Q : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_D : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_D1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_D2_PT_0 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_D2_PT_1 : STD_LOGIC; 
  signal Q_OpTx_FX_DC_79_D2 : STD_LOGIC; 
  signal clk10_count_15_Q : STD_LOGIC; 
  signal clk10_count_15_D : STD_LOGIC; 
  signal clk10_count_15_CLKF : STD_LOGIC; 
  signal clk10_count_15_CLKF_PT_0 : STD_LOGIC; 
  signal clk10_count_15_D1 : STD_LOGIC; 
  signal clk10_count_15_D2_PT_0 : STD_LOGIC; 
  signal clk10_count_15_D2 : STD_LOGIC; 
  signal clk10_count_15_D_TFF : STD_LOGIC; 
  signal clk10_count_15_EXP_PT_0 : STD_LOGIC; 
  signal clk10_count_17_Q : STD_LOGIC; 
  signal clk10_count_17_D : STD_LOGIC; 
  signal clk10_count_17_CLKF : STD_LOGIC; 
  signal clk10_count_17_CLKF_PT_0 : STD_LOGIC; 
  signal clk10_count_17_D1 : STD_LOGIC; 
  signal clk10_count_17_D2_PT_0 : STD_LOGIC; 
  signal clk10_count_17_D2 : STD_LOGIC; 
  signal clk10_count_17_D_TFF : STD_LOGIC; 
  signal EXP5_EXP : STD_LOGIC; 
  signal EXP4_EXP_PT_0 : STD_LOGIC; 
  signal EXP4_EXP_PT_1 : STD_LOGIC; 
  signal EXP4_EXP_PT_2 : STD_LOGIC; 
  signal EXP4_EXP_PT_3 : STD_LOGIC; 
  signal EXP4_EXP_PT_4 : STD_LOGIC; 
  signal EXP4_EXP_PT_5 : STD_LOGIC; 
  signal EXP5_EXP_PT_0 : STD_LOGIC; 
  signal EXP5_EXP_PT_1 : STD_LOGIC; 
  signal EXP5_EXP_PT_2 : STD_LOGIC; 
  signal EXP5_EXP_PT_3 : STD_LOGIC; 
  signal EXP5_EXP_PT_4 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_spk_obuf_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_spk_obuf_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_spk_obuf_EXP_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_spk_obuf_EXP_PT_2_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_spk_obuf_EXP_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_0_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_2_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_4_IN12 : STD_LOGIC; 
  signal NlwInverterSignal_EXP16_EXP_PT_4_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_1_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_2_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_D2_PT_3_IN11 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_1_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_0_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_0_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_0_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_0_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_tone_index_3_D2_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_4_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_5_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP3_EXP_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_1_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_2_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_3_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_3_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_3_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_4_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_5_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_EXP2_EXP_PT_5_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_EXP1_EXP_PT_0_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_SETF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_SETF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time2_2_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_SETF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_SETF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time2_4_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_RSTF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_RSTF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time2_6_EXP_PT_2_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_time1_1_SETF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_1_SETF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time1_1_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_RSTF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_RSTF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_time1_0_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_SETF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_SETF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_EXP_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_EXP_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_time1_2_EXP_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time1_5_RSTF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_5_RSTF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_SETF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_SETF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_time1_4_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_time1_3_RSTF_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_time1_3_RSTF_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_D2_PT_0_IN13 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_D2_PT_0_IN14 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_D2_PT_0_IN15 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_D2_PT_0_IN16 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_clk_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_cnt1_0_D2_PT_0_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_cnt1_0_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_count_14_EXP_PT_0_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_count_14_EXP_PT_1_IN8 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_count_14_EXP_PT_1_IN9 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_count_14_EXP_PT_1_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_clk10_count_14_EXP_PT_2_IN10 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_3_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_tone_count_3_D2_PT_1_IN0 : STD_LOGIC;