📄 music.tim
字号:
tone_count<10>.D 8.0
tone_count<1>.D 12.0
tone_count<2>.D 12.0
tone_count<3>.D 12.0
tone_count<4>.D 12.0
tone_count<5>.D 12.0
tone_count<6>.D 13.0
tone_count<7>.D 13.0
tone_count<8>.D 13.0
tone_count<9>.D 13.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk.Q)
\ From t t t t t t t t t t
\ o o o o o o o o o o
\ n n n n n n n n n n
\ e e e e e e e e e e
\ _ _ _ _ _ _ _ _ _ _
\ c c c c c c c c c c
\ o o o o o o o o o o
\ u u u u u u u u u u
\ n n n n n n n n n n
\ t t t t t t t t t t
\ < < < < < < < < < <
\ 1 1 2 3 4 5 6 7 8 9
\ 0 > > > > > > > > >
\ > . . . . . . . . .
\ . Q Q Q Q Q Q Q Q Q
\ Q
\
To \------------------------------------------------------------
clk10.D
clk10_count<10>.D
clk10_count<11>.D
clk10_count<12>.D
clk10_count<13>.D
clk10_count<14>.D
clk10_count<15>.D
clk10_count<16>.D
clk10_count<17>.D
clk10_count<1>.D
clk10_count<2>.D
clk10_count<3>.D
clk10_count<4>.D
clk10_count<5>.D
clk10_count<6>.D
clk10_count<7>.D
clk10_count<8>.D
clk10_count<9>.D
spk.D 13.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0
tone_count<0>.D 8.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0
tone_count<10>.D 8.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0
tone_count<1>.D 12.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
tone_count<2>.D 13.0 8.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0
tone_count<3>.D 13.0 8.0 8.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0
tone_count<4>.D 13.0 8.0 8.0 8.0 9.0 9.0 9.0 9.0 9.0 9.0
tone_count<5>.D 13.0 8.0 8.0 8.0 9.0 9.0 9.0 9.0 9.0 9.0
tone_count<6>.D 13.0 9.0 9.0 9.0 9.0 9.0 8.0 8.0 8.0 8.0
tone_count<7>.D 12.0 9.0 9.0 9.0 9.0 9.0 9.0 8.0 8.0 8.0
tone_count<8>.D 12.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 8.0 8.0
tone_count<9>.D 13.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 9.0 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk10.Q)
\ From t t t t t t t t t t
\ i i i i i i i i i i
\ m m m m m m m m m m
\ e e e e e e e e e e
\ 1 1 1 1 1 1 1 1 2 2
\ < < < < < < < < < <
\ 0 1 2 3 4 5 6 7 0 1
\ > > > > > > > > > >
\ . . . . . . . . . .
\ Q Q Q Q Q Q Q Q Q Q
\
\
\
\
\
To \------------------------------------------------------------
time1<0>.D 8.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0
time1<1>.D 12.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
time1<2>.D 12.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
time1<3>.D 12.0 8.0 8.0
time1<4>.D 12.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
time1<5>.D 12.0 8.0 8.0 8.0 8.0
time1<6>.D 12.0 8.0 8.0 8.0 8.0 8.0
time1<7>.D 12.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
time2<0>.D 9.0 9.0
time2<1>.D 8.0 9.0
time2<2>.D 9.0 9.0
time2<3>.D 8.0 8.0
time2<4>.D 9.0 9.0
time2<5>.D 8.0 8.0
time2<6>.D 9.0 9.0
time2<7>.D 9.0 9.0
tone_index<0>.D 22.5 22.5 34.0 34.0 13.0 34.0 34.0 23.5 36.0 24.5
tone_index<1>.D 10.0 14.0 14.0 13.0 14.0 14.0 14.0 15.0 15.0
tone_index<2>.D 22.5 22.5 22.5 22.5 12.0 24.5 15.0
tone_index<3>.D 10.0 10.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk10.Q)
\ From t t t t t t
\ i i i i i i
\ m m m m m m
\ e e e e e e
\ 2 2 2 2 2 2
\ < < < < < <
\ 2 3 4 5 6 7
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
\
\
\
\
\
To \------------------------------------
time1<0>.D
time1<1>.D
time1<2>.D
time1<3>.D
time1<4>.D
time1<5>.D
time1<6>.D
time1<7>.D
time2<0>.D 9.0 9.0 9.0 9.0 9.0 9.0
time2<1>.D 9.0 9.0 9.0 9.0 9.0 9.0
time2<2>.D 9.0 9.0 9.0 9.0 9.0 9.0
time2<3>.D 8.0
time2<4>.D 9.0 9.0 9.0 9.0 9.0 9.0
time2<5>.D 8.0 8.0 8.0
time2<6>.D 9.0 9.0 9.0 9.0
time2<7>.D 9.0 9.0 9.0 9.0 9.0 9.0
tone_index<0>.D 36.0 24.5 24.5 21.5 21.5 21.5
tone_index<1>.D 15.0 15.0 15.0 15.0 15.0 15.0
tone_index<2>.D 24.5 14.0 15.0 15.0 15.0 15.0
tone_index<3>.D 10.0 10.0 10.0 10.0 10.0 10.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU or tSUF) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and ends at register
(Fast Input Register for tSUF) D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers. Pin-to-pin setup
requirement is not reported or
guaranteed for product-term clocks
derived from macrocell feedback
signals.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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