📄 music.tim
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Performance Summary Report
--------------------------
Design: music
Device: XC95108-7-PC84
Speed File: Version 3.0
Program: Timing Report Generator: version F.28
Date: Mon Apr 20 16:07:08 2009
Performance Summary:
Clock net 'inclk' path delays:
Clock Pad to Output Pad (tCO) : 16.0ns (1 macrocell levels)
Clock Pad 'inclk' to Output Pad 'spk' (GCK)
Clock to Setup (tCYC) : 8.0ns (1 macrocell levels)
Clock to Q, net 'clk.Q' to DFF Setup(D) at 'clk.D' (GCK)
Target FF drives output net 'clk'
Minimum Clock Period: 8.0ns
Maximum Internal Clock Speed: 125.0Mhz
(Limited by Clock Pulse Width)
Clock net 'clk.Q' path delays:
Clock to Setup (tCYC) : 13.0ns (1 macrocell levels)
Clock to Q, net 'tone_count<0>.Q' to TFF Setup(D) at 'spk.D' (Pterm Clock)
Target FF drives output net 'spk_obuf$Q'
Minimum Clock Period: 13.0ns
Maximum Internal Clock Speed: 76.9Mhz
(Limited by Cycle Time)
Clock net 'clk10.Q' path delays:
Clock to Setup (tCYC) : 36.0ns (3 macrocell levels)
Clock to Q, net 'time2<0>.Q' to DFF Setup(D) at 'tone_index<0>.D' (Pterm Clock)
Target FF drives output net 'tone_index<0>'
Setup to Clock at the Pad (tSU) : 8.0ns (1 macrocell levels)
Data signal 'enable1' to DFF D input Pin at 'tone_index<0>.D'
Clock pad 'clk10.Q' (Pterm Clock)
Minimum Clock Period: 36.0ns
Maximum Internal Clock Speed: 27.7Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From i
\ n
\ c
\ l
\ k
\
\
To \------
spk 16.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: inclk)
\ From c c c c c c
\ l n n n n n
\ k t t t t t
\ . 1 1 1 1 1
\ Q < < < < <
\ 0 1 2 3 4
\ > > > > >
\ . . . . .
\ Q Q Q Q Q
To \------------------------------------
clk.D 8.0 8.0 8.0 8.0 8.0 8.0
cnt1<0>.D 8.0 8.0 8.0 8.0 8.0
cnt1<1>.D 8.0 8.0 8.0 8.0 8.0
cnt1<2>.D 8.0 8.0 8.0 8.0 8.0
cnt1<3>.D 8.0 8.0 8.0 8.0 8.0
cnt1<4>.D 8.0 8.0 8.0 8.0 8.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk.Q)
\ From c c c c c c c c c c
\ l l l l l l l l l l
\ k k k k k k k k k k
\ 1 1 1 1 1 1 1 1 1 1
\ 0 0 0 0 0 0 0 0 0 0
\ _ _ _ _ _ _ _ _ _ _
\ c c c c c c c c c c
\ o o o o o o o o o o
\ u u u u u u u u u u
\ n n n n n n n n n n
\ t t t t t t t t t t
\ < < < < < < < < < <
\ 0 1 1 1 1 1 1 1 1 1
\ > 0 1 2 3 4 5 6 7 >
\ . > > > > > > > > .
\ Q . . . . . . . . Q
\ Q Q Q Q Q Q Q Q
To \------------------------------------------------------------
clk10.D 12.0 8.0 8.0 8.0 8.0 12.0 12.0 8.0 8.0 8.0
clk10_count<10>.D 12.0 8.0
clk10_count<11>.D 12.0 8.0 8.0
clk10_count<12>.D 12.0 8.0 8.0 8.0
clk10_count<13>.D 12.0 8.0 8.0 8.0 8.0
clk10_count<14>.D 12.0 12.0 12.0 12.0 12.0 12.0
clk10_count<15>.D 12.0 12.0 12.0 12.0 12.0 8.0 12.0
clk10_count<16>.D 12.0 8.0 8.0 8.0 8.0 12.0 12.0 8.0
clk10_count<17>.D 12.0 8.0 8.0 8.0 8.0 12.0 12.0 8.0 8.0
clk10_count<1>.D 12.0
clk10_count<2>.D 12.0 8.0
clk10_count<3>.D 12.0 8.0
clk10_count<4>.D 12.0 8.0
clk10_count<5>.D 12.0 8.0
clk10_count<6>.D 12.0 8.0
clk10_count<7>.D 12.0 8.0
clk10_count<8>.D 12.0 8.0
clk10_count<9>.D 12.0 8.0
spk.D
tone_count<0>.D
tone_count<10>.D
tone_count<1>.D
tone_count<2>.D
tone_count<3>.D
tone_count<4>.D
tone_count<5>.D
tone_count<6>.D
tone_count<7>.D
tone_count<8>.D
tone_count<9>.D
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: clk.Q)
\ From c c c c c c c c s t
\ l l l l l l l l p o
\ k k k k k k k k k n
\ 1 1 1 1 1 1 1 1 . e
\ 0 0 0 0 0 0 0 0 Q _
\ _ _ _ _ _ _ _ _ c
\ c c c c c c c c o
\ o o o o o o o o u
\ u u u u u u u u n
\ n n n n n n n n t
\ t t t t t t t t <
\ < < < < < < < < 0
\ 2 3 4 5 6 7 8 9 >
\ > > > > > > > > .
\ . . . . . . . . Q
\ Q Q Q Q Q Q Q Q
\
To \------------------------------------------------------------
clk10.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<10>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<11>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<12>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<13>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<14>.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0
clk10_count<15>.D 12.0 12.0 12.0 12.0 12.0 12.0 12.0 12.0
clk10_count<16>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<17>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<1>.D
clk10_count<2>.D
clk10_count<3>.D 8.0
clk10_count<4>.D 8.0 8.0
clk10_count<5>.D 8.0 8.0 8.0
clk10_count<6>.D 8.0 8.0 8.0 8.0
clk10_count<7>.D 8.0 8.0 8.0 8.0 8.0
clk10_count<8>.D 8.0 8.0 8.0 8.0 8.0 8.0
clk10_count<9>.D 8.0 8.0 8.0 8.0 8.0 8.0 8.0
spk.D 8.0 13.0
tone_count<0>.D 8.0
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