music.syr

用CPLD做音乐发生器

Release 5.2i - xst F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: music.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : music.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : music
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Entity Name                        : music
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/music/music.vhd in Library work.
Entity <music> (Architecture <behave>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <music> (Architecture <behave>).
Entity <music> analyzed. Unit <music> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <music>.
    Related source file is F:/music/music.vhd.
    Found 16x11-bit ROM for signal <tone>.
    Found 128x4-bit ROM for signal <$n0023>.
    Found 1-bit register for signal <spk>.
    Found 5-bit comparator less for signal <$n0022> created at line 31.
    Found 12-bit comparator greatequal for signal <$n0288> created at line 390.
    Found 1-bit register for signal <clk>.
    Found 1-bit register for signal <clk10>.
    Found 18-bit up counter for signal <clk10_count>.
    Found 5-bit up counter for signal <cnt1>.
    Found 8-bit up counter for signal <time1>.
    Found 8-bit up counter for signal <time2>.
    Found 11-bit up counter for signal <tone_count>.
    Found 4-bit register for signal <tone_index>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 ROM(s).
	inferred   5 Counter(s).
	inferred   3 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <music> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
  16x11-bit ROM                    : 1
  128x4-bit ROM                    : 1
# Registers                        : 4
  1-bit register                   : 3
  4-bit register                   : 1
# Counters                         : 5
  5-bit up counter                 : 1
  18-bit up counter                : 1
  8-bit up counter                 : 2
  11-bit up counter                : 1
# Multiplexers                     : 1
  2-to-1 multiplexer               : 1
# Comparators                      : 2
  5-bit comparator less            : 1
  12-bit comparator greatequal     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <music> ...
  implementation constraint: INIT=r	 : cnt1_2
  implementation constraint: INIT=r	 : cnt1_0
  implementation constraint: INIT=r	 : time2_1
  implementation constraint: INIT=r	 : cnt1_3
  implementation constraint: INIT=r	 : time1_4
  implementation constraint: INIT=r	 : time2_4
  implementation constraint: INIT=r	 : tone_index_1
  implementation constraint: INIT=r	 : cnt1_1
  implementation constraint: INIT=r	 : time1_3
  implementation constraint: INIT=r	 : tone_index_3
  implementation constraint: INIT=r	 : tone_index_2
  implementation constraint: INIT=r	 : tone_index_0
  implementation constraint: INIT=r	 : time2_0
  implementation constraint: INIT=r	 : cnt1_4
  implementation constraint: INIT=r	 : time2_2
  implementation constraint: INIT=r	 : time2_3
  implementation constraint: INIT=r	 : time1_5
  implementation constraint: INIT=r	 : time1_7
  implementation constraint: INIT=r	 : time1_6
  implementation constraint: INIT=r	 : time1_0
  implementation constraint: INIT=r	 : time1_1
  implementation constraint: INIT=r	 : time1_2
  implementation constraint: INIT=r	 : time2_5
  implementation constraint: INIT=r	 : time2_7
  implementation constraint: INIT=r	 : time2_6

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : music.ngr
Top Level Output File Name         : music
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : YES
Macro Generator                    : macro+
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 4

Macro Statistics :
# Registers                        : 69
#      1-bit register              : 69
# Xors                             : 50
#      1-bit xor2                  : 50

Cell Usage :
# BELS                             : 1022
#      AND2                        : 323
#      AND3                        : 65
#      AND4                        : 34
#      AND5                        : 7
#      AND6                        : 5
#      AND7                        : 6
#      AND8                        : 17
#      INV                         : 377
#      OR2                         : 114
#      OR3                         : 19
#      XOR2                        : 55
# FlipFlops/Latches                : 57
#      FD                          : 41
#      FDC                         : 8
#      FDP                         : 8
# IO Buffers                       : 4
#      IBUF                        : 3
#      OBUF                        : 1
=========================================================================
CPU : 44.80 / 45.81 s | Elapsed : 44.00 / 45.00 s
 
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Total memory usage is 59856 kilobytes