led7.vhd

来自「EDA」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
entity led7 is
	port( ledin : in  std_logic_vector(3 downto 0);
		 ledout : out std_logic_vector(6 downto 0);
			clk_led7 : in std_logic);
end led7;

architecture behav of led7 is
begin
com1:process(clk_led7) 
begin
	if (clk_led7'event and clk_led7='1') then
	case ledin is
	when "0000" => ledout<="1000000";--0
	when "0001" => ledout<="1111001";--1
	when "0010" => ledout<="0100100";--2
	when "0011" => ledout<="0110000";--3
	when "0100" => ledout<="0011001";--4
	when "0101" => ledout<="0010010";--5
	when "0110" => ledout<="0000010";--6
	when "0111" => ledout<="1111000";--7
	when "1000" => ledout<="0000000";--8
	when "1001" => ledout<="0010000";--9
	when others => ledout<="1111111";--nothing
	end case;
	end if;
 end process com1;
end behav;