led7.tan.qmsg

EDA

{ "Info" "ITDB_TSU_RESULT" "ledout\[6\]~reg0 ledin\[2\] clk_led7 1.048 ns register " "Info: tsu for register \"ledout\[6\]~reg0\" (data pin = \"ledin\[2\]\", clock pin = \"clk_led7\") is 1.048 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.789 ns + Longest pin register " "Info: + Longest pin to register delay is 3.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns ledin\[2\] 1 PIN PIN_P25 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 7; PIN Node = 'ledin\[2\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[2] } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.268 ns) + CELL(0.438 ns) 3.705 ns Mux0~23 2 COMB LCCOMB_X28_Y3_N16 1 " "Info: 2: + IC(2.268 ns) + CELL(0.438 ns) = 3.705 ns; Loc. = LCCOMB_X28_Y3_N16; Fanout = 1; COMB Node = 'Mux0~23'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.706 ns" { ledin[2] Mux0~23 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.789 ns ledout\[6\]~reg0 3 REG LCFF_X28_Y3_N17 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.789 ns; Loc. = LCFF_X28_Y3_N17; Fanout = 1; REG Node = 'ledout\[6\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux0~23 ledout[6]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.521 ns ( 40.14 % ) " "Info: Total cell delay = 1.521 ns ( 40.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.268 ns ( 59.86 % ) " "Info: Total interconnect delay = 2.268 ns ( 59.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.789 ns" { ledin[2] Mux0~23 ledout[6]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.789 ns" { ledin[2] {} ledin[2]~combout {} Mux0~23 {} ledout[6]~reg0 {} } { 0.000ns 0.000ns 2.268ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led7 destination 2.705 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_led7\" to destination register is 2.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_led7 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_led7 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_led7~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_led7 clk_led7~clkctrl } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.537 ns) 2.705 ns ledout\[6\]~reg0 3 REG LCFF_X28_Y3_N17 1 " "Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N17; Fanout = 1; REG Node = 'ledout\[6\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { clk_led7~clkctrl ledout[6]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.78 % ) " "Info: Total cell delay = 1.536 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.169 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.169 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[6]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[6]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.789 ns" { ledin[2] Mux0~23 ledout[6]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.789 ns" { ledin[2] {} ledin[2]~combout {} Mux0~23 {} ledout[6]~reg0 {} } { 0.000ns 0.000ns 2.268ns 0.000ns } { 0.000ns 0.999ns 0.438ns 0.084ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[6]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[6]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_led7 ledout\[0\] ledout\[0\]~reg0 6.686 ns register " "Info: tco from clock \"clk_led7\" to destination pin \"ledout\[0\]\" through register \"ledout\[0\]~reg0\" is 6.686 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led7 source 2.705 ns + Longest register " "Info: + Longest clock path from clock \"clk_led7\" to source register is 2.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_led7 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_led7 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_led7~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_led7 clk_led7~clkctrl } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.537 ns) 2.705 ns ledout\[0\]~reg0 3 REG LCFF_X28_Y3_N25 1 " "Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N25; Fanout = 1; REG Node = 'ledout\[0\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { clk_led7~clkctrl ledout[0]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.78 % ) " "Info: Total cell delay = 1.536 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.169 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.169 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[0]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.731 ns + Longest register pin " "Info: + Longest register to pin delay is 3.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledout\[0\]~reg0 1 REG LCFF_X28_Y3_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y3_N25; Fanout = 1; REG Node = 'ledout\[0\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledout[0]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.933 ns) + CELL(2.798 ns) 3.731 ns ledout\[0\] 2 PIN PIN_AF10 0 " "Info: 2: + IC(0.933 ns) + CELL(2.798 ns) = 3.731 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'ledout\[0\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.731 ns" { ledout[0]~reg0 ledout[0] } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 74.99 % ) " "Info: Total cell delay = 2.798 ns ( 74.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.933 ns ( 25.01 % ) " "Info: Total interconnect delay = 0.933 ns ( 25.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.731 ns" { ledout[0]~reg0 ledout[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.731 ns" { ledout[0]~reg0 {} ledout[0] {} } { 0.000ns 0.933ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[0]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.731 ns" { ledout[0]~reg0 ledout[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.731 ns" { ledout[0]~reg0 {} ledout[0] {} } { 0.000ns 0.933ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ledout\[2\]~reg0 ledin\[3\] clk_led7 0.440 ns register " "Info: th for register \"ledout\[2\]~reg0\" (data pin = \"ledin\[3\]\", clock pin = \"clk_led7\") is 0.440 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_led7 destination 2.705 ns + Longest register " "Info: + Longest clock path from clock \"clk_led7\" to destination register is 2.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_led7 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_led7 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_led7~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_led7 clk_led7~clkctrl } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.537 ns) 2.705 ns ledout\[2\]~reg0 3 REG LCFF_X28_Y3_N5 1 " "Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N5; Fanout = 1; REG Node = 'ledout\[2\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.588 ns" { clk_led7~clkctrl ledout[2]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.78 % ) " "Info: Total cell delay = 1.536 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.169 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.169 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[2]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.531 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.531 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns ledin\[3\] 1 PIN PIN_AE14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 7; PIN Node = 'ledin\[3\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[3] } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.275 ns) 2.447 ns Mux4~19 2 COMB LCCOMB_X28_Y3_N4 1 " "Info: 2: + IC(1.173 ns) + CELL(0.275 ns) = 2.447 ns; Loc. = LCCOMB_X28_Y3_N4; Fanout = 1; COMB Node = 'Mux4~19'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.448 ns" { ledin[3] Mux4~19 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.531 ns ledout\[2\]~reg0 3 REG LCFF_X28_Y3_N5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.531 ns; Loc. = LCFF_X28_Y3_N5; Fanout = 1; REG Node = 'ledout\[2\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux4~19 ledout[2]~reg0 } "NODE_NAME" } } { "led7.vhd" "" { Text "D:/study/VHDL/led7/led7.vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.358 ns ( 53.65 % ) " "Info: Total cell delay = 1.358 ns ( 53.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.173 ns ( 46.35 % ) " "Info: Total interconnect delay = 1.173 ns ( 46.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.531 ns" { ledin[3] Mux4~19 ledout[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.531 ns" { ledin[3] {} ledin[3]~combout {} Mux4~19 {} ledout[2]~reg0 {} } { 0.000ns 0.000ns 1.173ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.705 ns" { clk_led7 clk_led7~clkctrl ledout[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.705 ns" { clk_led7 {} clk_led7~combout {} clk_led7~clkctrl {} ledout[2]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.051ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.531 ns" { ledin[3] Mux4~19 ledout[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.531 ns" { ledin[3] {} ledin[3]~combout {} Mux4~19 {} ledout[2]~reg0 {} } { 0.000ns 0.000ns 1.173ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 15 19:17:34 2009 " "Info: Processing ended: Fri May 15 19:17:34 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}