led7.tan.rpt

来自「EDA」· RPT 代码 · 共 233 行 · 第 1/2 页

; N/A   ; None         ; -0.207 ns  ; ledin[3] ; ledout[5]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.210 ns  ; ledin[3] ; ledout[2]~reg0 ; clk_led7 ;
; N/A   ; None         ; -0.210 ns  ; ledin[3] ; ledout[4]~reg0 ; clk_led7 ;
+-------+--------------+------------+----------+----------------+----------+


+-----------------------------------------------------------------------------+
; tco                                                                         ;
+-------+--------------+------------+----------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From           ; To        ; From Clock ;
+-------+--------------+------------+----------------+-----------+------------+
; N/A   ; None         ; 6.686 ns   ; ledout[0]~reg0 ; ledout[0] ; clk_led7   ;
; N/A   ; None         ; 6.664 ns   ; ledout[1]~reg0 ; ledout[1] ; clk_led7   ;
; N/A   ; None         ; 6.660 ns   ; ledout[2]~reg0 ; ledout[2] ; clk_led7   ;
; N/A   ; None         ; 6.431 ns   ; ledout[4]~reg0 ; ledout[4] ; clk_led7   ;
; N/A   ; None         ; 6.430 ns   ; ledout[3]~reg0 ; ledout[3] ; clk_led7   ;
; N/A   ; None         ; 6.420 ns   ; ledout[5]~reg0 ; ledout[5] ; clk_led7   ;
; N/A   ; None         ; 6.419 ns   ; ledout[6]~reg0 ; ledout[6] ; clk_led7   ;
+-------+--------------+------------+----------------+-----------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+----------+----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To             ; To Clock ;
+---------------+-------------+-----------+----------+----------------+----------+
; N/A           ; None        ; 0.440 ns  ; ledin[3] ; ledout[2]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.440 ns  ; ledin[3] ; ledout[4]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.437 ns  ; ledin[3] ; ledout[5]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.433 ns  ; ledin[3] ; ledout[1]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.432 ns  ; ledin[3] ; ledout[0]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.431 ns  ; ledin[3] ; ledout[3]~reg0 ; clk_led7 ;
; N/A           ; None        ; 0.430 ns  ; ledin[3] ; ledout[6]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.309 ns ; ledin[0] ; ledout[4]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.311 ns ; ledin[0] ; ledout[1]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.311 ns ; ledin[0] ; ledout[5]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.312 ns ; ledin[0] ; ledout[0]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.312 ns ; ledin[0] ; ledout[2]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.312 ns ; ledin[0] ; ledout[3]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.313 ns ; ledin[0] ; ledout[6]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.623 ns ; ledin[1] ; ledout[5]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.624 ns ; ledin[1] ; ledout[2]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.624 ns ; ledin[1] ; ledout[4]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.626 ns ; ledin[1] ; ledout[0]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.627 ns ; ledin[1] ; ledout[1]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.629 ns ; ledin[1] ; ledout[3]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.630 ns ; ledin[1] ; ledout[6]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.812 ns ; ledin[2] ; ledout[4]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.812 ns ; ledin[2] ; ledout[5]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.813 ns ; ledin[2] ; ledout[2]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.815 ns ; ledin[2] ; ledout[1]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.816 ns ; ledin[2] ; ledout[0]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.817 ns ; ledin[2] ; ledout[3]~reg0 ; clk_led7 ;
; N/A           ; None        ; -0.818 ns ; ledin[2] ; ledout[6]~reg0 ; clk_led7 ;
+---------------+-------------+-----------+----------+----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri May 15 19:17:33 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led7 -c led7 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_led7" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk_led7"
Info: tsu for register "ledout[6]~reg0" (data pin = "ledin[2]", clock pin = "clk_led7") is 1.048 ns
    Info: + Longest pin to register delay is 3.789 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P25; Fanout = 7; PIN Node = 'ledin[2]'
        Info: 2: + IC(2.268 ns) + CELL(0.438 ns) = 3.705 ns; Loc. = LCCOMB_X28_Y3_N16; Fanout = 1; COMB Node = 'Mux0~23'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.789 ns; Loc. = LCFF_X28_Y3_N17; Fanout = 1; REG Node = 'ledout[6]~reg0'
        Info: Total cell delay = 1.521 ns ( 40.14 % )
        Info: Total interconnect delay = 2.268 ns ( 59.86 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk_led7" to destination register is 2.705 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'
        Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N17; Fanout = 1; REG Node = 'ledout[6]~reg0'
        Info: Total cell delay = 1.536 ns ( 56.78 % )
        Info: Total interconnect delay = 1.169 ns ( 43.22 % )
Info: tco from clock "clk_led7" to destination pin "ledout[0]" through register "ledout[0]~reg0" is 6.686 ns
    Info: + Longest clock path from clock "clk_led7" to source register is 2.705 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'
        Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N25; Fanout = 1; REG Node = 'ledout[0]~reg0'
        Info: Total cell delay = 1.536 ns ( 56.78 % )
        Info: Total interconnect delay = 1.169 ns ( 43.22 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.731 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y3_N25; Fanout = 1; REG Node = 'ledout[0]~reg0'
        Info: 2: + IC(0.933 ns) + CELL(2.798 ns) = 3.731 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'ledout[0]'
        Info: Total cell delay = 2.798 ns ( 74.99 % )
        Info: Total interconnect delay = 0.933 ns ( 25.01 % )
Info: th for register "ledout[2]~reg0" (data pin = "ledin[3]", clock pin = "clk_led7") is 0.440 ns
    Info: + Longest clock path from clock "clk_led7" to destination register is 2.705 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_led7'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk_led7~clkctrl'
        Info: 3: + IC(1.051 ns) + CELL(0.537 ns) = 2.705 ns; Loc. = LCFF_X28_Y3_N5; Fanout = 1; REG Node = 'ledout[2]~reg0'
        Info: Total cell delay = 1.536 ns ( 56.78 % )
        Info: Total interconnect delay = 1.169 ns ( 43.22 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.531 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 7; PIN Node = 'ledin[3]'
        Info: 2: + IC(1.173 ns) + CELL(0.275 ns) = 2.447 ns; Loc. = LCCOMB_X28_Y3_N4; Fanout = 1; COMB Node = 'Mux4~19'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.531 ns; Loc. = LCFF_X28_Y3_N5; Fanout = 1; REG Node = 'ledout[2]~reg0'
        Info: Total cell delay = 1.358 ns ( 53.65 % )
        Info: Total interconnect delay = 1.173 ns ( 46.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Fri May 15 19:17:34 2009
    Info: Elapsed time: 00:00:01