keymove.tan.qmsg

EDA

{ "Info" "ITDB_TSU_RESULT" "key_out1\[1\] keyin\[1\] keyclk 6.520 ns register " "Info: tsu for register \"key_out1\[1\]\" (data pin = \"keyin\[1\]\", clock pin = \"keyclk\") is 6.520 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.237 ns + Longest pin register " "Info: + Longest pin to register delay is 9.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyin\[1\] 1 PIN PIN_N26 5 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 5; PIN Node = 'keyin\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[1] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.199 ns) + CELL(0.371 ns) 3.569 ns Equal2~75 2 COMB LCCOMB_X32_Y2_N4 4 " "Info: 2: + IC(2.199 ns) + CELL(0.371 ns) = 3.569 ns; Loc. = LCCOMB_X32_Y2_N4; Fanout = 4; COMB Node = 'Equal2~75'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.570 ns" { keyin[1] Equal2~75 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.282 ns) + CELL(0.275 ns) 4.126 ns Equal0~62 3 COMB LCCOMB_X32_Y2_N2 1 " "Info: 3: + IC(0.282 ns) + CELL(0.275 ns) = 4.126 ns; Loc. = LCCOMB_X32_Y2_N2; Fanout = 1; COMB Node = 'Equal0~62'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.557 ns" { Equal2~75 Equal0~62 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.487 ns) + CELL(0.437 ns) 5.050 ns Equal9~61 4 COMB LCCOMB_X32_Y2_N20 2 " "Info: 4: + IC(0.487 ns) + CELL(0.437 ns) = 5.050 ns; Loc. = LCCOMB_X32_Y2_N20; Fanout = 2; COMB Node = 'Equal9~61'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.924 ns" { Equal0~62 Equal9~61 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.420 ns) 5.927 ns WideNor0~138 5 COMB LCCOMB_X31_Y2_N26 1 " "Info: 5: + IC(0.457 ns) + CELL(0.420 ns) = 5.927 ns; Loc. = LCCOMB_X31_Y2_N26; Fanout = 1; COMB Node = 'WideNor0~138'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.877 ns" { Equal9~61 WideNor0~138 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.420 ns) 7.013 ns WideNor0 6 COMB LCCOMB_X33_Y2_N22 2 " "Info: 6: + IC(0.666 ns) + CELL(0.420 ns) = 7.013 ns; Loc. = LCCOMB_X33_Y2_N22; Fanout = 2; COMB Node = 'WideNor0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.086 ns" { WideNor0~138 WideNor0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.721 ns) + CELL(0.275 ns) 8.009 ns WideOr2~14 7 COMB LCCOMB_X31_Y2_N12 2 " "Info: 7: + IC(0.721 ns) + CELL(0.275 ns) = 8.009 ns; Loc. = LCCOMB_X31_Y2_N12; Fanout = 2; COMB Node = 'WideOr2~14'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.996 ns" { WideNor0 WideOr2~14 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.438 ns) 9.153 ns WideOr2 8 COMB LCCOMB_X33_Y2_N14 1 " "Info: 8: + IC(0.706 ns) + CELL(0.438 ns) = 9.153 ns; Loc. = LCCOMB_X33_Y2_N14; Fanout = 1; COMB Node = 'WideOr2'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.144 ns" { WideOr2~14 WideOr2 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.237 ns key_out1\[1\] 9 REG LCFF_X33_Y2_N15 9 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 9.237 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr2 key_out1[1] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.719 ns ( 40.26 % ) " "Info: Total cell delay = 3.719 ns ( 40.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.518 ns ( 59.74 % ) " "Info: Total interconnect delay = 5.518 ns ( 59.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.237 ns" { keyin[1] Equal2~75 Equal0~62 Equal9~61 WideNor0~138 WideNor0 WideOr2~14 WideOr2 key_out1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "9.237 ns" { keyin[1] {} keyin[1]~combout {} Equal2~75 {} Equal0~62 {} Equal9~61 {} WideNor0~138 {} WideNor0 {} WideOr2~14 {} WideOr2 {} key_out1[1] {} } { 0.000ns 0.000ns 2.199ns 0.282ns 0.487ns 0.457ns 0.666ns 0.721ns 0.706ns 0.000ns } { 0.000ns 0.999ns 0.371ns 0.275ns 0.437ns 0.420ns 0.420ns 0.275ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk destination 2.681 ns - Shortest register " "Info: - Shortest clock path from clock \"keyclk\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns key_out1\[1\] 3 REG LCFF_X33_Y2_N15 9 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { keyclk~clkctrl key_out1[1] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { keyclk keyclk~clkctrl key_out1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[1] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "9.237 ns" { keyin[1] Equal2~75 Equal0~62 Equal9~61 WideNor0~138 WideNor0 WideOr2~14 WideOr2 key_out1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "9.237 ns" { keyin[1] {} keyin[1]~combout {} Equal2~75 {} Equal0~62 {} Equal9~61 {} WideNor0~138 {} WideNor0 {} WideOr2~14 {} WideOr2 {} key_out1[1] {} } { 0.000ns 0.000ns 2.199ns 0.282ns 0.487ns 0.457ns 0.666ns 0.721ns 0.706ns 0.000ns } { 0.000ns 0.999ns 0.371ns 0.275ns 0.437ns 0.420ns 0.420ns 0.275ns 0.438ns 0.084ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { keyclk keyclk~clkctrl key_out1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[1] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "keyclk keyout3\[2\] keyout3\[2\]~reg0 8.391 ns register " "Info: tco from clock \"keyclk\" to destination pin \"keyout3\[2\]\" through register \"keyout3\[2\]~reg0\" is 8.391 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk source 2.694 ns + Longest register " "Info: + Longest clock path from clock \"keyclk\" to source register is 2.694 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.537 ns) 2.694 ns keyout3\[2\]~reg0 3 REG LCFF_X61_Y4_N9 1 " "Info: 3: + IC(1.040 ns) + CELL(0.537 ns) = 2.694 ns; Loc. = LCFF_X61_Y4_N9; Fanout = 1; REG Node = 'keyout3\[2\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { keyclk~clkctrl keyout3[2]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.02 % ) " "Info: Total cell delay = 1.536 ns ( 57.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.158 ns ( 42.98 % ) " "Info: Total interconnect delay = 1.158 ns ( 42.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.694 ns" { keyclk keyclk~clkctrl keyout3[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.694 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout3[2]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.040ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.447 ns + Longest register pin " "Info: + Longest register to pin delay is 5.447 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyout3\[2\]~reg0 1 REG LCFF_X61_Y4_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y4_N9; Fanout = 1; REG Node = 'keyout3\[2\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyout3[2]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.649 ns) + CELL(2.798 ns) 5.447 ns keyout3\[2\] 2 PIN PIN_AE12 0 " "Info: 2: + IC(2.649 ns) + CELL(2.798 ns) = 5.447 ns; Loc. = PIN_AE12; Fanout = 0; PIN Node = 'keyout3\[2\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.447 ns" { keyout3[2]~reg0 keyout3[2] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 51.37 % ) " "Info: Total cell delay = 2.798 ns ( 51.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.649 ns ( 48.63 % ) " "Info: Total interconnect delay = 2.649 ns ( 48.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.447 ns" { keyout3[2]~reg0 keyout3[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.447 ns" { keyout3[2]~reg0 {} keyout3[2] {} } { 0.000ns 2.649ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.694 ns" { keyclk keyclk~clkctrl keyout3[2]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.694 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout3[2]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.040ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "5.447 ns" { keyout3[2]~reg0 keyout3[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "5.447 ns" { keyout3[2]~reg0 {} keyout3[2] {} } { 0.000ns 2.649ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "key_out1\[0\] keyin\[3\] keyclk 0.662 ns register " "Info: th for register \"key_out1\[0\]\" (data pin = \"keyin\[3\]\", clock pin = \"keyclk\") is 0.662 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk destination 2.681 ns + Longest register " "Info: + Longest clock path from clock \"keyclk\" to destination register is 2.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.681 ns key_out1\[0\] 3 REG LCFF_X33_Y2_N9 9 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N9; Fanout = 9; REG Node = 'key_out1\[0\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.29 % ) " "Info: Total cell delay = 1.536 ns ( 57.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 42.71 % ) " "Info: Total interconnect delay = 1.145 ns ( 42.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { keyclk keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[0] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.285 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyin\[3\] 1 PIN PIN_AE14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 5; PIN Node = 'keyin\[3\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[3] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.804 ns) + CELL(0.398 ns) 2.201 ns WideOr3~80 2 COMB LCCOMB_X33_Y2_N8 2 " "Info: 2: + IC(0.804 ns) + CELL(0.398 ns) = 2.201 ns; Loc. = LCCOMB_X33_Y2_N8; Fanout = 2; COMB Node = 'WideOr3~80'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.202 ns" { keyin[3] WideOr3~80 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.285 ns key_out1\[0\] 3 REG LCFF_X33_Y2_N9 9 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.285 ns; Loc. = LCFF_X33_Y2_N9; Fanout = 9; REG Node = 'key_out1\[0\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr3~80 key_out1[0] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.481 ns ( 64.81 % ) " "Info: Total cell delay = 1.481 ns ( 64.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.804 ns ( 35.19 % ) " "Info: Total interconnect delay = 0.804 ns ( 35.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.285 ns" { keyin[3] WideOr3~80 key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.285 ns" { keyin[3] {} keyin[3]~combout {} WideOr3~80 {} key_out1[0] {} } { 0.000ns 0.000ns 0.804ns 0.000ns } { 0.000ns 0.999ns 0.398ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { keyclk keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.681 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[0] {} } { 0.000ns 0.000ns 0.118ns 1.027ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.285 ns" { keyin[3] WideOr3~80 key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.285 ns" { keyin[3] {} keyin[3]~combout {} WideOr3~80 {} key_out1[0] {} } { 0.000ns 0.000ns 0.804ns 0.000ns } { 0.000ns 0.999ns 0.398ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}