prev_cmp_keymove.tan.qmsg

EDA

{ "Info" "ITDB_TSU_RESULT" "keyout4\[0\]~reg0 OE keyclk 5.656 ns register " "Info: tsu for register \"keyout4\[0\]~reg0\" (data pin = \"OE\", clock pin = \"keyclk\") is 5.656 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.387 ns + Longest pin register " "Info: + Longest pin to register delay is 8.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns OE 1 PIN PIN_V2 32 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 32; PIN Node = 'OE'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { OE } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.875 ns) + CELL(0.660 ns) 8.387 ns keyout4\[0\]~reg0 2 REG LCFF_X64_Y4_N1 1 " "Info: 2: + IC(6.875 ns) + CELL(0.660 ns) = 8.387 ns; Loc. = LCFF_X64_Y4_N1; Fanout = 1; REG Node = 'keyout4\[0\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "7.535 ns" { OE keyout4[0]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.512 ns ( 18.03 % ) " "Info: Total cell delay = 1.512 ns ( 18.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.875 ns ( 81.97 % ) " "Info: Total interconnect delay = 6.875 ns ( 81.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.387 ns" { OE keyout4[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "8.387 ns" { OE {} OE~combout {} keyout4[0]~reg0 {} } { 0.000ns 0.000ns 6.875ns } { 0.000ns 0.852ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk destination 2.695 ns - Shortest register " "Info: - Shortest clock path from clock \"keyclk\" to destination register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns keyout4\[0\]~reg0 3 REG LCFF_X64_Y4_N1 1 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X64_Y4_N1; Fanout = 1; REG Node = 'keyout4\[0\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { keyclk~clkctrl keyout4[0]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { keyclk keyclk~clkctrl keyout4[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout4[0]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "8.387 ns" { OE keyout4[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "8.387 ns" { OE {} OE~combout {} keyout4[0]~reg0 {} } { 0.000ns 0.000ns 6.875ns } { 0.000ns 0.852ns 0.660ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { keyclk keyclk~clkctrl keyout4[0]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout4[0]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "keyclk keyout1\[1\] keyout1\[1\]~reg0 9.190 ns register " "Info: tco from clock \"keyclk\" to destination pin \"keyout1\[1\]\" through register \"keyout1\[1\]~reg0\" is 9.190 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk source 2.674 ns + Longest register " "Info: + Longest clock path from clock \"keyclk\" to source register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns keyout1\[1\]~reg0 3 REG LCFF_X34_Y4_N9 1 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X34_Y4_N9; Fanout = 1; REG Node = 'keyout1\[1\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.557 ns" { keyclk~clkctrl keyout1[1]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { keyclk keyclk~clkctrl keyout1[1]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout1[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.266 ns + Longest register pin " "Info: + Longest register to pin delay is 6.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyout1\[1\]~reg0 1 REG LCFF_X34_Y4_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y4_N9; Fanout = 1; REG Node = 'keyout1\[1\]~reg0'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyout1[1]~reg0 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.468 ns) + CELL(2.798 ns) 6.266 ns keyout1\[1\] 2 PIN PIN_AD21 0 " "Info: 2: + IC(3.468 ns) + CELL(2.798 ns) = 6.266 ns; Loc. = PIN_AD21; Fanout = 0; PIN Node = 'keyout1\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.266 ns" { keyout1[1]~reg0 keyout1[1] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 44.65 % ) " "Info: Total cell delay = 2.798 ns ( 44.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.468 ns ( 55.35 % ) " "Info: Total interconnect delay = 3.468 ns ( 55.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.266 ns" { keyout1[1]~reg0 keyout1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.266 ns" { keyout1[1]~reg0 {} keyout1[1] {} } { 0.000ns 3.468ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { keyclk keyclk~clkctrl keyout1[1]~reg0 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} keyout1[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.266 ns" { keyout1[1]~reg0 keyout1[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.266 ns" { keyout1[1]~reg0 {} keyout1[1] {} } { 0.000ns 3.468ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "key_out1\[0\] keyin\[3\] keyclk 0.825 ns register " "Info: th for register \"key_out1\[0\]\" (data pin = \"keyin\[3\]\", clock pin = \"keyclk\") is 0.825 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "keyclk destination 2.674 ns + Longest register " "Info: + Longest clock path from clock \"keyclk\" to destination register is 2.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyclk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyclk } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns keyclk~clkctrl 2 COMB CLKCTRL_G2 48 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { keyclk keyclk~clkctrl } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.020 ns) + CELL(0.537 ns) 2.674 ns key_out1\[0\] 3 REG LCFF_X34_Y4_N5 9 " "Info: 3: + IC(1.020 ns) + CELL(0.537 ns) = 2.674 ns; Loc. = LCFF_X34_Y4_N5; Fanout = 9; REG Node = 'key_out1\[0\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.557 ns" { keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.44 % ) " "Info: Total cell delay = 1.536 ns ( 57.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.138 ns ( 42.56 % ) " "Info: Total interconnect delay = 1.138 ns ( 42.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { keyclk keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.115 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyin\[3\] 1 PIN PIN_AE14 5 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 5; PIN Node = 'keyin\[3\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keyin[3] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.661 ns) + CELL(0.371 ns) 2.031 ns WideOr3~80 2 COMB LCCOMB_X34_Y4_N4 2 " "Info: 2: + IC(0.661 ns) + CELL(0.371 ns) = 2.031 ns; Loc. = LCCOMB_X34_Y4_N4; Fanout = 2; COMB Node = 'WideOr3~80'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.032 ns" { keyin[3] WideOr3~80 } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.115 ns key_out1\[0\] 3 REG LCFF_X34_Y4_N5 9 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.115 ns; Loc. = LCFF_X34_Y4_N5; Fanout = 9; REG Node = 'key_out1\[0\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr3~80 key_out1[0] } "NODE_NAME" } } { "keymove.vhd" "" { Text "D:/study/VHDL/keymove/keymove.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 68.75 % ) " "Info: Total cell delay = 1.454 ns ( 68.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.661 ns ( 31.25 % ) " "Info: Total interconnect delay = 0.661 ns ( 31.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { keyin[3] WideOr3~80 key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.115 ns" { keyin[3] {} keyin[3]~combout {} WideOr3~80 {} key_out1[0] {} } { 0.000ns 0.000ns 0.661ns 0.000ns } { 0.000ns 0.999ns 0.371ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.674 ns" { keyclk keyclk~clkctrl key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.674 ns" { keyclk {} keyclk~combout {} keyclk~clkctrl {} key_out1[0] {} } { 0.000ns 0.000ns 0.118ns 1.020ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { keyin[3] WideOr3~80 key_out1[0] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.115 ns" { keyin[3] {} keyin[3]~combout {} WideOr3~80 {} key_out1[0] {} } { 0.000ns 0.000ns 0.661ns 0.000ns } { 0.000ns 0.999ns 0.371ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}