📄 keymove.tan.rpt
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; N/A ; None ; -2.033 ns ; keyin[7] ; key_out1[1] ; keyclk ;
; N/A ; None ; -2.036 ns ; keyin[9] ; key_out1[3] ; keyclk ;
; N/A ; None ; -2.055 ns ; keyin[8] ; key_out1[2] ; keyclk ;
; N/A ; None ; -2.116 ns ; keyin[0] ; key_out1[1] ; keyclk ;
; N/A ; None ; -2.194 ns ; keyin[8] ; key_out1[1] ; keyclk ;
; N/A ; None ; -2.236 ns ; keyin[2] ; key_out1[0] ; keyclk ;
; N/A ; None ; -2.239 ns ; keyin[9] ; key_out1[1] ; keyclk ;
; N/A ; None ; -2.278 ns ; keyin[2] ; key_out1[3] ; keyclk ;
; N/A ; None ; -2.287 ns ; keyin[0] ; key_out1[0] ; keyclk ;
; N/A ; None ; -2.398 ns ; keyin[9] ; key_out1[2] ; keyclk ;
; N/A ; None ; -2.431 ns ; keyin[1] ; key_out1[3] ; keyclk ;
; N/A ; None ; -4.241 ns ; OE ; key_out4[3] ; keymove ;
; N/A ; None ; -4.241 ns ; OE ; key_out3[3] ; keymove ;
; N/A ; None ; -4.241 ns ; OE ; key_out2[3] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out4[0] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out3[0] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out2[0] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out4[1] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out3[1] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out2[1] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out4[2] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out3[2] ; keymove ;
; N/A ; None ; -4.262 ns ; OE ; key_out2[2] ; keymove ;
; N/A ; None ; -4.703 ns ; OE ; key_out1[0] ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; key_out1[1] ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; key_out1[2] ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; key_out1[3] ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; keyout1[0]~reg0 ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; keyout1[1]~reg0 ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; keyout1[2]~reg0 ; keyclk ;
; N/A ; None ; -4.703 ns ; OE ; keyout1[3]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout4[0]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout4[1]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout4[2]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout4[3]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout3[0]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout3[1]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout3[2]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout3[3]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout2[0]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout2[1]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout2[2]~reg0 ; keyclk ;
; N/A ; None ; -5.195 ns ; OE ; keyout2[3]~reg0 ; keyclk ;
+---------------+-------------+-----------+----------+-----------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri May 15 22:50:44 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keymove -c keymove --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "keyclk" is an undefined clock
Info: Assuming node "keymove" is an undefined clock
Info: Clock "keyclk" Internal fmax is restricted to 420.17 MHz between source register "key_out1[1]" and destination register "led7:u1|ledout[3]"
Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.082 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1[1]'
Info: 2: + IC(0.560 ns) + CELL(0.438 ns) = 0.998 ns; Loc. = LCCOMB_X33_Y2_N18; Fanout = 1; COMB Node = 'led7:u1|Mux3~23'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.082 ns; Loc. = LCFF_X33_Y2_N19; Fanout = 1; REG Node = 'led7:u1|ledout[3]'
Info: Total cell delay = 0.522 ns ( 48.24 % )
Info: Total interconnect delay = 0.560 ns ( 51.76 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "keyclk" to destination register is 2.681 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'
Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N19; Fanout = 1; REG Node = 'led7:u1|ledout[3]'
Info: Total cell delay = 1.536 ns ( 57.29 % )
Info: Total interconnect delay = 1.145 ns ( 42.71 % )
Info: - Longest clock path from clock "keyclk" to source register is 2.681 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'
Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1[1]'
Info: Total cell delay = 1.536 ns ( 57.29 % )
Info: Total interconnect delay = 1.145 ns ( 42.71 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Micro setup delay of destination is -0.036 ns
Info: Clock "keymove" Internal fmax is restricted to 450.05 MHz between source register "key_out3[0]" and destination register "key_out4[0]"
Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.628 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X64_Y4_N23; Fanout = 9; REG Node = 'key_out3[0]'
Info: 2: + IC(0.395 ns) + CELL(0.149 ns) = 0.544 ns; Loc. = LCCOMB_X64_Y4_N4; Fanout = 1; COMB Node = 'key_out4[0]~feeder'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.628 ns; Loc. = LCFF_X64_Y4_N5; Fanout = 8; REG Node = 'key_out4[0]'
Info: Total cell delay = 0.233 ns ( 37.10 % )
Info: Total interconnect delay = 0.395 ns ( 62.90 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "keymove" to destination register is 3.629 ns
Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 12; CLK Node = 'keymove'
Info: 2: + IC(2.230 ns) + CELL(0.537 ns) = 3.629 ns; Loc. = LCFF_X64_Y4_N5; Fanout = 8; REG Node = 'key_out4[0]'
Info: Total cell delay = 1.399 ns ( 38.55 % )
Info: Total interconnect delay = 2.230 ns ( 61.45 % )
Info: - Longest clock path from clock "keymove" to source register is 3.629 ns
Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 12; CLK Node = 'keymove'
Info: 2: + IC(2.230 ns) + CELL(0.537 ns) = 3.629 ns; Loc. = LCFF_X64_Y4_N23; Fanout = 9; REG Node = 'key_out3[0]'
Info: Total cell delay = 1.399 ns ( 38.55 % )
Info: Total interconnect delay = 2.230 ns ( 61.45 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "key_out1[1]" (data pin = "keyin[1]", clock pin = "keyclk") is 6.520 ns
Info: + Longest pin to register delay is 9.237 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N26; Fanout = 5; PIN Node = 'keyin[1]'
Info: 2: + IC(2.199 ns) + CELL(0.371 ns) = 3.569 ns; Loc. = LCCOMB_X32_Y2_N4; Fanout = 4; COMB Node = 'Equal2~75'
Info: 3: + IC(0.282 ns) + CELL(0.275 ns) = 4.126 ns; Loc. = LCCOMB_X32_Y2_N2; Fanout = 1; COMB Node = 'Equal0~62'
Info: 4: + IC(0.487 ns) + CELL(0.437 ns) = 5.050 ns; Loc. = LCCOMB_X32_Y2_N20; Fanout = 2; COMB Node = 'Equal9~61'
Info: 5: + IC(0.457 ns) + CELL(0.420 ns) = 5.927 ns; Loc. = LCCOMB_X31_Y2_N26; Fanout = 1; COMB Node = 'WideNor0~138'
Info: 6: + IC(0.666 ns) + CELL(0.420 ns) = 7.013 ns; Loc. = LCCOMB_X33_Y2_N22; Fanout = 2; COMB Node = 'WideNor0'
Info: 7: + IC(0.721 ns) + CELL(0.275 ns) = 8.009 ns; Loc. = LCCOMB_X31_Y2_N12; Fanout = 2; COMB Node = 'WideOr2~14'
Info: 8: + IC(0.706 ns) + CELL(0.438 ns) = 9.153 ns; Loc. = LCCOMB_X33_Y2_N14; Fanout = 1; COMB Node = 'WideOr2'
Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 9.237 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1[1]'
Info: Total cell delay = 3.719 ns ( 40.26 % )
Info: Total interconnect delay = 5.518 ns ( 59.74 % )
Info: + Micro setup delay of destination is -0.036 ns
Info: - Shortest clock path from clock "keyclk" to destination register is 2.681 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'
Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N15; Fanout = 9; REG Node = 'key_out1[1]'
Info: Total cell delay = 1.536 ns ( 57.29 % )
Info: Total interconnect delay = 1.145 ns ( 42.71 % )
Info: tco from clock "keyclk" to destination pin "keyout3[2]" through register "keyout3[2]~reg0" is 8.391 ns
Info: + Longest clock path from clock "keyclk" to source register is 2.694 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'
Info: 3: + IC(1.040 ns) + CELL(0.537 ns) = 2.694 ns; Loc. = LCFF_X61_Y4_N9; Fanout = 1; REG Node = 'keyout3[2]~reg0'
Info: Total cell delay = 1.536 ns ( 57.02 % )
Info: Total interconnect delay = 1.158 ns ( 42.98 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Longest register to pin delay is 5.447 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X61_Y4_N9; Fanout = 1; REG Node = 'keyout3[2]~reg0'
Info: 2: + IC(2.649 ns) + CELL(2.798 ns) = 5.447 ns; Loc. = PIN_AE12; Fanout = 0; PIN Node = 'keyout3[2]'
Info: Total cell delay = 2.798 ns ( 51.37 % )
Info: Total interconnect delay = 2.649 ns ( 48.63 % )
Info: th for register "key_out1[0]" (data pin = "keyin[3]", clock pin = "keyclk") is 0.662 ns
Info: + Longest clock path from clock "keyclk" to destination register is 2.681 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'keyclk'
Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 48; COMB Node = 'keyclk~clkctrl'
Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.681 ns; Loc. = LCFF_X33_Y2_N9; Fanout = 9; REG Node = 'key_out1[0]'
Info: Total cell delay = 1.536 ns ( 57.29 % )
Info: Total interconnect delay = 1.145 ns ( 42.71 % )
Info: + Micro hold delay of destination is 0.266 ns
Info: - Shortest pin to register delay is 2.285 ns
Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 5; PIN Node = 'keyin[3]'
Info: 2: + IC(0.804 ns) + CELL(0.398 ns) = 2.201 ns; Loc. = LCCOMB_X33_Y2_N8; Fanout = 2; COMB Node = 'WideOr3~80'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.285 ns; Loc. = LCFF_X33_Y2_N9; Fanout = 9; REG Node = 'key_out1[0]'
Info: Total cell delay = 1.481 ns ( 64.81 % )
Info: Total interconnect delay = 0.804 ns ( 35.19 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 116 megabytes of memory during processing
Info: Processing ended: Fri May 15 22:50:44 2009
Info: Elapsed time: 00:00:00
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