lock.map.qmsg

EDA

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "add\[1\] lock.vhd(48) " "Info (10041): Inferred latch for \"add\[1\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "add\[2\] lock.vhd(48) " "Info (10041): Inferred latch for \"add\[2\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password4\[0\] lock.vhd(48) " "Info (10041): Inferred latch for \"password4\[0\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password4\[1\] lock.vhd(48) " "Info (10041): Inferred latch for \"password4\[1\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password4\[2\] lock.vhd(48) " "Info (10041): Inferred latch for \"password4\[2\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password4\[3\] lock.vhd(48) " "Info (10041): Inferred latch for \"password4\[3\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password3\[0\] lock.vhd(48) " "Info (10041): Inferred latch for \"password3\[0\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password3\[1\] lock.vhd(48) " "Info (10041): Inferred latch for \"password3\[1\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password3\[2\] lock.vhd(48) " "Info (10041): Inferred latch for \"password3\[2\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password3\[3\] lock.vhd(48) " "Info (10041): Inferred latch for \"password3\[3\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password2\[0\] lock.vhd(48) " "Info (10041): Inferred latch for \"password2\[0\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password2\[1\] lock.vhd(48) " "Info (10041): Inferred latch for \"password2\[1\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password2\[2\] lock.vhd(48) " "Info (10041): Inferred latch for \"password2\[2\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password2\[3\] lock.vhd(48) " "Info (10041): Inferred latch for \"password2\[3\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password1\[0\] lock.vhd(48) " "Info (10041): Inferred latch for \"password1\[0\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password1\[1\] lock.vhd(48) " "Info (10041): Inferred latch for \"password1\[1\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password1\[2\] lock.vhd(48) " "Info (10041): Inferred latch for \"password1\[2\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "password1\[3\] lock.vhd(48) " "Info (10041): Inferred latch for \"password1\[3\]\" at lock.vhd(48)" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keymove keymove:u1 " "Info: Elaborating entity \"keymove\" for hierarchy \"keymove:u1\"" {  } { { "lock.vhd" "u1" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 80 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "keyreset keymove.vhd(32) " "Warning (10492): VHDL Process Statement warning at keymove.vhd(32): signal \"keyreset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clear keymove.vhd(32) " "Warning (10492): VHDL Process Statement warning at keymove.vhd(32): signal \"clear\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led7 keymove:u1\|led7:u1 " "Info: Elaborating entity \"led7\" for hierarchy \"keymove:u1\|led7:u1\"" {  } { { "../keymove/keymove.vhd" "u1" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|lock\|current_state 6 " "Info: State machine \"\|lock\|current_state\" contains 6 states" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|lock\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|lock\|current_state\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|lock\|current_state " "Info: Encoding result for state machine \"\|lock\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st5 " "Info: Encoded state bit \"current_state.st5\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st4 " "Info: Encoded state bit \"current_state.st4\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st3 " "Info: Encoded state bit \"current_state.st3\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st2 " "Info: Encoded state bit \"current_state.st2\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st1 " "Info: Encoded state bit \"current_state.st1\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "current_state.st0 " "Info: Encoded state bit \"current_state.st0\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st0 000000 " "Info: State \"\|lock\|current_state.st0\" uses code string \"000000\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st1 000011 " "Info: State \"\|lock\|current_state.st1\" uses code string \"000011\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st2 000101 " "Info: State \"\|lock\|current_state.st2\" uses code string \"000101\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st3 001001 " "Info: State \"\|lock\|current_state.st3\" uses code string \"001001\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st4 010001 " "Info: State \"\|lock\|current_state.st4\" uses code string \"010001\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|lock\|current_state.st5 100001 " "Info: State \"\|lock\|current_state.st5\" uses code string \"100001\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 32 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "177 " "Info: Implemented 177 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Info: Implemented 30 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "132 " "Info: Implemented 132 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 20 20:42:22 2009 " "Info: Processing ended: Wed May 20 20:42:22 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}