lock.tan.qmsg

EDA

{ "Info" "ITDB_FULL_TCO_RESULT" "clk led7_out4\[6\] keymove:u1\|led7:u4\|ledout\[6\] 8.490 ns register " "Info: tco from clock \"clk\" to destination pin \"led7_out4\[6\]\" through register \"keymove:u1\|led7:u4\|ledout\[6\]\" is 8.490 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.657 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.657 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.537 ns) 2.657 ns keymove:u1\|led7:u4\|ledout\[6\] 3 REG LCFF_X37_Y8_N25 1 " "Info: 3: + IC(1.003 ns) + CELL(0.537 ns) = 2.657 ns; Loc. = LCFF_X37_Y8_N25; Fanout = 1; REG Node = 'keymove:u1\|led7:u4\|ledout\[6\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.540 ns" { clk~clkctrl keymove:u1|led7:u4|ledout[6] } "NODE_NAME" } } { "../led7/led7.vhd" "" { Text "D:/study/VHDL/lock_cipher/led7/led7.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.81 % ) " "Info: Total cell delay = 1.536 ns ( 57.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.121 ns ( 42.19 % ) " "Info: Total interconnect delay = 1.121 ns ( 42.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.657 ns" { clk clk~clkctrl keymove:u1|led7:u4|ledout[6] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/qu