lock.tan.qmsg

EDA

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "current_state.st2 " "Info: Detected ripple clock \"current_state.st2\" as buffer" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "current_state.st2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "current_state.st5 " "Info: Detected ripple clock \"current_state.st5\" as buffer" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "current_state.st5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register password2\[2\] register current_state.st4 84.72 MHz 11.804 ns Internal " "Info: Clock \"clk\" has Internal fmax of 84.72 MHz between source register \"password2\[2\]\" and destination register \"current_state.st4\" (period= 11.804 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.258 ns + Longest register register " "Info: + Longest register to register delay is 2.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns password2\[2\] 1 REG LCCOMB_X34_Y8_N26 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X34_Y8_N26; Fanout = 1; REG Node = 'password2\[2\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { password2[2] } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.275 ns) 0.720 ns com~123 2 COMB LCCOMB_X34_Y8_N18 1 " "Info: 2: + IC(0.445 ns) + CELL(0.275 ns) = 0.720 ns; Loc. = LCCOMB_X34_Y8_N18; Fanout = 1; COMB Node = 'com~123'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.720 ns" { password2[2] com~123 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.393 ns) 1.372 ns com~125 3 COMB LCCOMB_X34_Y8_N10 1 " "Info: 3: + IC(0.259 ns) + CELL(0.393 ns) = 1.372 ns; Loc. = LCCOMB_X34_Y8_N10; Fanout = 1; COMB Node = 'com~125'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { com~123 com~125 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.150 ns) 1.776 ns com~2 4 COMB LCCOMB_X34_Y8_N0 2 " "Info: 4: + IC(0.254 ns) + CELL(0.150 ns) = 1.776 ns; Loc. = LCCOMB_X34_Y8_N0; Fanout = 2; COMB Node = 'com~2'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.404 ns" { com~125 com~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 2.174 ns Selector6~8 5 COMB LCCOMB_X34_Y8_N28 1 " "Info: 5: + IC(0.248 ns) + CELL(0.150 ns) = 2.174 ns; Loc. = LCCOMB_X34_Y8_N28; Fanout = 1; COMB Node = 'Selector6~8'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.398 ns" { com~2 Selector6~8 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.258 ns current_state.st4 6 REG LCFF_X34_Y8_N29 4 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.258 ns; Loc. = LCFF_X34_Y8_N29; Fanout = 4; REG Node = 'current_state.st4'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { Selector6~8 current_state.st4 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.052 ns ( 46.59 % ) " "Info: Total cell delay = 1.052 ns ( 46.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.206 ns ( 53.41 % ) " "Info: Total interconnect delay = 1.206 ns ( 53.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.258 ns" { password2[2] com~123 com~125 com~2 Selector6~8 current_state.st4 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.258 ns" { password2[2] {} com~123 {} com~125 {} com~2 {} Selector6~8 {} current_state.st4 {} } { 0.000ns 0.445ns 0.259ns 0.254ns 0.248ns 0.000ns } { 0.000ns 0.275ns 0.393ns 0.150ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.680 ns - Smallest " "Info: - Smallest clock skew is -3.680 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.650 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 52 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 52; COMB Node = 'clk~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.537 ns) 2.650 ns current_state.st4 3 REG LCFF_X34_Y8_N29 4 " "Info: 3: + IC(0.996 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X34_Y8_N29; Fanout = 4; REG Node = 'current_state.st4'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.533 ns" { clk~clkctrl current_state.st4 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.96 % ) " "Info: Total cell delay = 1.536 ns ( 57.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.114 ns ( 42.04 % ) " "Info: Total interconnect delay = 1.114 ns ( 42.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { clk clk~clkctrl current_state.st4 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.st4 {} } { 0.000ns 0.000ns 0.118ns 0.996ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.330 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'clk'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.905 ns) + CELL(0.787 ns) 3.691 ns current_state.st2 2 REG LCFF_X34_Y7_N9 4 " "Info: 2: + IC(1.905 ns) + CELL(0.787 ns) = 3.691 ns; Loc. = LCFF_X34_Y7_N9; Fanout = 4; REG Node = 'current_state.st2'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.692 ns" { clk current_state.st2 } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.130 ns) + CELL(0.000 ns) 4.821 ns current_state.st2~clkctrl 3 COMB CLKCTRL_G15 16 " "Info: 3: + IC(1.130 ns) + CELL(0.000 ns) = 4.821 ns; Loc. = CLKCTRL_G15; Fanout = 16; COMB Node = 'current_state.st2~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { current_state.st2 current_state.st2~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.359 ns) + CELL(0.150 ns) 6.330 ns password2\[2\] 4 REG LCCOMB_X34_Y8_N26 1 " "Info: 4: + IC(1.359 ns) + CELL(0.150 ns) = 6.330 ns; Loc. = LCCOMB_X34_Y8_N26; Fanout = 1; REG Node = 'password2\[2\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.509 ns" { current_state.st2~clkctrl password2[2] } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 30.58 % ) " "Info: Total cell delay = 1.936 ns ( 30.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.394 ns ( 69.42 % ) " "Info: Total interconnect delay = 4.394 ns ( 69.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk current_state.st2 current_state.st2~clkctrl password2[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[2] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.359ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { clk clk~clkctrl current_state.st4 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.st4 {} } { 0.000ns 0.000ns 0.118ns 0.996ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk current_state.st2 current_state.st2~clkctrl password2[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[2] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.359ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.150ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 27 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.258 ns" { password2[2] com~123 com~125 com~2 Selector6~8 current_state.st4 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.258 ns" { password2[2] {} com~123 {} com~125 {} com~2 {} Selector6~8 {} current_state.st4 {} } { 0.000ns 0.445ns 0.259ns 0.254ns 0.248ns 0.000ns } { 0.000ns 0.275ns 0.393ns 0.150ns 0.150ns 0.084ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.650 ns" { clk clk~clkctrl current_state.st4 } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.650 ns" { clk {} clk~combout {} clk~clkctrl {} current_state.st4 {} } { 0.000ns 0.000ns 0.118ns 0.996ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "6.330 ns" { clk current_state.st2 current_state.st2~clkctrl password2[2] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "6.330 ns" { clk {} clk~combout {} current_state.st2 {} current_state.st2~clkctrl {} password2[2] {} } { 0.000ns 0.000ns 1.905ns 1.130ns 1.359ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.150ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "move register register keymove:u1\|key_out3\[1\] keymove:u1\|key_out4\[1\] 450.05 MHz Internal " "Info: Clock \"move\" Internal fmax is restricted to 450.05 MHz between source register \"keymove:u1\|key_out3\[1\]\" and destination register \"keymove:u1\|key_out4\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.594 ns + Longest register register " "Info: + Longest register to register delay is 0.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keymove:u1\|key_out3\[1\] 1 REG LCFF_X36_Y8_N11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y8_N11; Fanout = 9; REG Node = 'keymove:u1\|key_out3\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keymove:u1|key_out3[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.149 ns) 0.510 ns keymove:u1\|key_out4\[1\]~feeder 2 COMB LCCOMB_X36_Y8_N4 1 " "Info: 2: + IC(0.361 ns) + CELL(0.149 ns) = 0.510 ns; Loc. = LCCOMB_X36_Y8_N4; Fanout = 1; COMB Node = 'keymove:u1\|key_out4\[1\]~feeder'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.510 ns" { keymove:u1|key_out3[1] keymove:u1|key_out4[1]~feeder } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.594 ns keymove:u1\|key_out4\[1\] 3 REG LCFF_X36_Y8_N5 8 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.594 ns; Loc. = LCFF_X36_Y8_N5; Fanout = 8; REG Node = 'keymove:u1\|key_out4\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { keymove:u1|key_out4[1]~feeder keymove:u1|key_out4[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.233 ns ( 39.23 % ) " "Info: Total cell delay = 0.233 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.361 ns ( 60.77 % ) " "Info: Total interconnect delay = 0.361 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.594 ns" { keymove:u1|key_out3[1] keymove:u1|key_out4[1]~feeder keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "0.594 ns" { keymove:u1|key_out3[1] {} keymove:u1|key_out4[1]~feeder {} keymove:u1|key_out4[1] {} } { 0.000ns 0.361ns 0.000ns } { 0.000ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "move destination 2.560 ns + Shortest register " "Info: + Shortest clock path from clock \"move\" to destination register is 2.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns move 1 CLK PIN_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 3; CLK Node = 'move'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { move } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.041 ns) + CELL(0.155 ns) 1.038 ns move~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G4 1 " "Info: 2: + IC(0.041 ns) + CELL(0.155 ns) = 1.038 ns; Loc. = CLKDELAYCTRL_G4; Fanout = 1; COMB Node = 'move~clk_delay_ctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.196 ns" { move move~clk_delay_ctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.038 ns move~clkctrl 3 COMB CLKCTRL_G4 12 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G4; Fanout = 12; COMB Node = 'move~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { move~clk_delay_ctrl move~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.537 ns) 2.560 ns keymove:u1\|key_out4\[1\] 4 REG LCFF_X36_Y8_N5 8 " "Info: 4: + IC(0.985 ns) + CELL(0.537 ns) = 2.560 ns; Loc. = LCFF_X36_Y8_N5; Fanout = 8; REG Node = 'keymove:u1\|key_out4\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { move~clkctrl keymove:u1|key_out4[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.534 ns ( 59.92 % ) " "Info: Total cell delay = 1.534 ns ( 59.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 40.08 % ) " "Info: Total interconnect delay = 1.026 ns ( 40.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out4[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "move source 2.560 ns - Longest register " "Info: - Longest clock path from clock \"move\" to source register is 2.560 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns move 1 CLK PIN_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_N23; Fanout = 3; CLK Node = 'move'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { move } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.041 ns) + CELL(0.155 ns) 1.038 ns move~clk_delay_ctrl 2 COMB CLKDELAYCTRL_G4 1 " "Info: 2: + IC(0.041 ns) + CELL(0.155 ns) = 1.038 ns; Loc. = CLKDELAYCTRL_G4; Fanout = 1; COMB Node = 'move~clk_delay_ctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.196 ns" { move move~clk_delay_ctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.038 ns move~clkctrl 3 COMB CLKCTRL_G4 12 " "Info: 3: + IC(0.000 ns) + CELL(0.000 ns) = 1.038 ns; Loc. = CLKCTRL_G4; Fanout = 12; COMB Node = 'move~clkctrl'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { move~clk_delay_ctrl move~clkctrl } "NODE_NAME" } } { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.985 ns) + CELL(0.537 ns) 2.560 ns keymove:u1\|key_out3\[1\] 4 REG LCFF_X36_Y8_N11 9 " "Info: 4: + IC(0.985 ns) + CELL(0.537 ns) = 2.560 ns; Loc. = LCFF_X36_Y8_N11; Fanout = 9; REG Node = 'keymove:u1\|key_out3\[1\]'" {  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { move~clkctrl keymove:u1|key_out3[1] } "NODE_NAME" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.534 ns ( 59.92 % ) " "Info: Total cell delay = 1.534 ns ( 59.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns ( 40.08 % ) " "Info: Total interconnect delay = 1.026 ns ( 40.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out3[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out3[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out4[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out3[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out3[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.594 ns" { keymove:u1|key_out3[1] keymove:u1|key_out4[1]~feeder keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "0.594 ns" { keymove:u1|key_out3[1] {} keymove:u1|key_out4[1]~feeder {} keymove:u1|key_out4[1] {} } { 0.000ns 0.361ns 0.000ns } { 0.000ns 0.149ns 0.084ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out4[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.560 ns" { move move~clk_delay_ctrl move~clkctrl keymove:u1|key_out3[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.560 ns" { move {} move~combout {} move~clk_delay_ctrl {} move~clkctrl {} keymove:u1|key_out3[1] {} } { 0.000ns 0.000ns 0.041ns 0.000ns 0.985ns } { 0.000ns 0.842ns 0.155ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { keymove:u1|key_out4[1] } "NODE_NAME" } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { keymove:u1|key_out4[1] {} } {  } {  } "" } } { "../keymove/keymove.vhd" "" { Text "D:/study/VHDL/lock_cipher/keymove/keymove.vhd" 26 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}