lock.tan.qmsg

EDA

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "password4\[2\] " "Warning: Node \"password4\[2\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password1\[2\] " "Warning: Node \"password1\[2\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password1\[3\] " "Warning: Node \"password1\[3\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password4\[1\] " "Warning: Node \"password4\[1\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password1\[1\] " "Warning: Node \"password1\[1\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "add\[2\] " "Warning: Node \"add\[2\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "add\[1\] " "Warning: Node \"add\[1\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password4\[3\] " "Warning: Node \"password4\[3\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password2\[3\] " "Warning: Node \"password2\[3\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password4\[0\] " "Warning: Node \"password4\[0\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password3\[2\] " "Warning: Node \"password3\[2\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password3\[3\] " "Warning: Node \"password3\[3\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password2\[2\] " "Warning: Node \"password2\[2\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password2\[0\] " "Warning: Node \"password2\[0\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password3\[1\] " "Warning: Node \"password3\[1\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password3\[0\] " "Warning: Node \"password3\[0\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password1\[0\] " "Warning: Node \"password1\[0\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "password2\[1\] " "Warning: Node \"password2\[1\]\" is a latch" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "add\[0\]~18 " "Warning: Node \"add\[0\]~18\"" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 48 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 5 -1 0 } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "move " "Info: Assuming node \"move\" is an undefined clock" {  } { { "lock.vhd" "" { Text "D:/study/VHDL/lock_cipher/lock/lock.vhd" 7 -1 0 } } { "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/study/eda-quartus7.2/eda-quartus7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "move" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}