lock.vhd.bak

EDA

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lock is
port( clk : in std_logic;
	  key : in std_logic_vector(9 downto 0); 
	 move,enter,reset,initialization : in std_logic;
	led_ok,led_wrong : out std_logic;
	led7_out1,led7_out2,led7_out3,led7_out4 : out std_logic_vector(6 downto 0));
end entity lock;

architecture behav of lock is

  component led7
	port( ledin : in  std_logic_vector(3 downto 0);
		 ledout : out std_logic_vector(6 downto 0);
			clk_led7 : in std_logic);
  end component;
  component keymove
	port(keyin : in std_logic_vector(9 downto 0);
		keyclk,keymove,OE,keyreset,clear: in std_logic;
		keyout4,keyout3,keyout2,keyout1 : out std_logic_vector(3 downto 0);	
	led_out1,led_out2,led_out3,led_out4 : out std_logic_vector(6 downto 0));
  end component;

type state is (st0,st1,st2,st3,st4,st5);
signal current_state,next_state : state;
signal ledout1,ledout2,ledout3,ledout4 : std_logic_vector(6 downto 0);
signal key_out4,key_out3,key_out2,key_out1 : std_logic_vector(3 downto 0);
signal OES,kreset : std_logic;
signal password1,password2,password3,password4 : std_logic_vector(3 downto 0):="0000";
--signal password2 : std_logic_vector(3 downto 0):="0000";
--signal password3 : std_logic_vector(3 downto 0):="0000";
--signal password4 : std_logic_vector(3 downto 0):="0000";
signal add : std_logic_vector(1 downto 0);

signal password_h : std_logic_vector(3 downto 0);

begin
 reg:process(reset,clk)
  begin
	if reset = '0' then current_state<=st0;
	elsif clk'event and clk = '1' then
		current_state<=next_state;
	end if;
  end process reg;
	
 com : process(current_state,clk)
  begin
	case current_state is
	when st0=>OES<='0';kreset<='0';kreset<='1';led_ok<='0';led_wrong<='0';
				if (move='0') then next_state<=st1;
--				elsif (initialization='0') then next_state<=st2;
				else next_state<=st0;
				end if;								
	when st1=>led_ok<='0';led_wrong<='0';OES<='1';kreset<='0';
				if enter='0' then next_state<=st3;
				else next_state<=st1;
				end if;				
	when st2=>OES<='1'; led_ok<='0';led_wrong<='0';kreset<='0';password1<=key_out1;password2<=key_out2;password3<=key_out3;password4<=key_out4;
				if enter='0' then OES<='0';next_state<=st0;
				else next_state<=st2;
				end if;
	when st3=>OES<='0'; led_ok<='0';led_wrong<='0';kreset<='0';
			if((key_out1=password1)and(key_out2=password2)and(key_out3=password3)and(key_out4=password4))
			   then  next_state<=st4;
			   else  next_state<=st5; 
				end if;
	when st4=>led_ok<='1';led_wrong<='0';OES<='0';--1 is open
		if (initialization='0') then kreset<='1';next_state<=st2;
		else kreset<='0';next_state<=st4;
		end if;
		
	when st5=>led_ok<='0';led_wrong<='1';OES<='0';kreset<='1';add<= add + 1;next_state<=st5;
		if (add="11") then next_state<=st3;
		end if;
	end case;	
  end process com;

  u1 : keymove port map (keyin=>key,keyclk=>clk,keymove=>move,OE=>OES,keyreset=>reset,clear=>kreset,keyout4=>key_out4,keyout3=>key_out3,keyout2=>key_out2,keyout1=>key_out1,led_out1=>led7_out1,led_out2=>led7_out2,led_out3=>led7_out3,led_out4=>led7_out4);

end architecture behav;