lock.fit.rpt

来自「EDA」· RPT 代码 · 共 463 行 · 第 1/5 页

; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/study/VHDL/lock_cipher/lock/lock.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 131 / 33,216 ( < 1 % ) ;
;     -- Combinational with no register       ; 65                     ;
;     -- Register only                        ; 12                     ;
;     -- Combinational with a register        ; 54                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 67                     ;
;     -- 3 input functions                    ; 30                     ;
;     -- <=2 input functions                  ; 22                     ;
;     -- Register only                        ; 12                     ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 119                    ;
;     -- arithmetic mode                      ; 0                      ;
;                                             ;                        ;
; Total registers*                            ; 66 / 34,593 ( < 1 % )  ;
;     -- Dedicated logic registers            ; 66 / 33,216 ( < 1 % )  ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )      ;
;                                             ;                        ;
; Total LABs:  partially or completely used   ; 10 / 2,076 ( < 1 % )   ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 45 / 475 ( 9 % )       ;
;     -- Clock pins                           ; 7 / 8 ( 88 % )         ;
; Global signals                              ; 6                      ;
; M4Ks                                        ; 0 / 105 ( 0 % )        ;
; Total memory bits                           ; 0 / 483,840 ( 0 % )    ;
; Total RAM block bits                        ; 0 / 483,840 ( 0 % )    ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )         ;
; PLLs                                        ; 0 / 4 ( 0 % )          ;
; Global clocks                               ; 6 / 16 ( 38 % )        ;
; Average interconnect usage                  ; 0%                     ;
; Peak interconnect usage                     ; 1%                     ;
; Maximum fan-out node                        ; clk~clkctrl            ;
; Maximum fan-out                             ; 52                     ;
; Highest non-global fan-out signal           ; Selector0~8            ;
; Highest non-global fan-out                  ; 32                     ;
; Total fan-out                               ; 620                    ;
; Average fan-out                             ; 2.47                   ;
+---------------------------------------------+------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                           ;
+----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name           ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+