sdcard.h

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#endif

// 120-125, 6 reserved bits
#define SD_CSD_TAAC_BIT_SLICE               112
#define SD_CSD_TAAC_SLICE_SIZE              8
#define SD_CSD_NSAC_BIT_SLICE               104
#define SD_CSD_NSAC_SLICE_SIZE              8
#define SD_CSD_TRANS_SPEED_BIT_SLICE        96
#define SD_CSD_TRANS_SPEED_SLICE_SIZE       8
#define SD_CSD_CCC_BIT_SLICE                84
#define SD_CSD_CCC_SLICE_SIZE               12
#define SD_CSD_READ_BL_LEN_BIT_SLICE        80
#define SD_CSD_READ_BL_LEN_SLICE_SIZE       4
#define SD_CSD_READ_BL_PARTIAL_BIT_SLICE    79
#define SD_CSD_READ_BL_PARTIAL_SLICE_SIZE   1
#define SD_CSD_WRITE_BL_MISALIGN_BIT_SLICE  78
#define SD_CSD_WRITE_BL_MISALIGN_SLICE_SIZE 1
#define SD_CSD_READ_BL_MISALIGN_BIT_SLICE   77
#define SD_CSD_READ_BL_MISALIGN_SLICE_SIZE  1
#define SD_CSD_DSR_IMP_BIT_SLICE            76
#define SD_CSD_DSR_IMP_SLICE_SIZE           1
// 74-75, 2 reserved bits
#define SD_CSD_CSIZE_BIT_SLICE              62
#define SD_CSD_CSIZE_SLICE_SIZE             12
#define SD_CSD20_CSIZE_BIT_SLICE            48
#define SD_CSD20_CSIZE_SLICE_SIZE           22
#define SD_CSD_R_CURR_MIN_BIT_SLICE         59
#define SD_CSD_R_CURR_MIN_SLICE_SIZE        3
#define SD_CSD_R_CURR_MAX_BIT_SLICE         56
#define SD_CSD_R_CURR_MAX_SLICE_SIZE        3      
#define SD_CSD_W_CURR_MIN_BIT_SLICE         53
#define SD_CSD_W_CURR_MIN_SLICE_SIZE        3
#define SD_CSD_W_CURR_MAX_BIT_SLICE         50
#define SD_CSD_W_CURR_MAX_SLICE_SIZE        3
#define SD_CSD_CSIZE_MULT_BIT_SLICE         47
#define SD_CSD_CSIZE_MULT_SLICE_SIZE        3
#define SD_CSD_ERASE_BL_ENABLE_BIT_SLICE    46
#define SD_CSD_ERASE_BL_ENABLE_SLICE_SIZE   1
#define SD_CSD_ERASE_SECT_SIZE_BIT_SLICE    39
#define SD_CSD_ERASE_SECT_SIZE_SLICE_SIZE   7
#define SD_CSD_WP_GROUP_SIZE_BIT_SLICE      32
#define SD_CSD_WP_GROUP_SIZE_SLICE_SIZE     7
#define SD_CSD_WP_GRP_ENABLE_BIT_SLICE      31
#define SD_CSD_WP_GRP_ENABLE_SLICE_SIZE     1 
// 29-30, 3 reserved bits
#define SD_CSD_R2W_FACTOR_BIT_SLICE         26
#define SD_CSD_R2W_FACTOR_SLICE_SIZE        3
#define SD_CSD_WRITE_BL_LEN_BIT_SLICE       22
#define SD_CSD_WRITE_BL_LEN_SLICE_SIZE      4
#define SD_CSD_WRITE_BL_PARTIAL_BIT_SLICE   21
#define SD_CSD_WRITE_BL_PARTIAL_SLICE_SIZE  1
// 16-20, 5 reserved bits
#define SD_CSD_FILE_GROUP_BIT_SLICE         15
#define SD_CSD_FILE_GROUP_SLICE_SIZE        1
#define SD_CSD_COPY_FLAG_BIT_SLICE          14
#define SD_CSD_COPY_FLAG_SLICE_SIZE         1 
#define SD_CSD_PERM_WR_PROT_BIT_SLICE       13
#define SD_CSD_PERM_WR_PROT_SLICE_SIZE      1
#define SD_CSD_TEMP_WR_PROT_BIT_SLICE       12
#define SD_CSD_TEMP_WR_PROT_SLICE_SIZE      1
#define SD_CSD_FILE_FORMAT_BIT_SLICE        10 
#define SD_CSD_FILE_FORMAT_SLICE_SIZE       2
// 8-9, 2 reserved bits
#define SD_CSD_CRC_BIT_SLICE                1
#define SD_CSD_CRC_SLICE_SIZE               7

// CSD Card Command Classes (CCC)
#define SD_CSD_CCC_BASIC                    (0 << 0)
#define SD_CSD_CCC_RESERVED1                (1 << 1)
#define SD_CSD_CCC_BLOCK_READ               (1 << 2)
#define SD_CSD_CCC_RESERVED3                (1 << 3)
#define SD_CSD_CCC_BLOCK_WRITE              (1 << 4)
#define SD_CSD_CCC_ERASE                    (1 << 5)
#define SD_CSD_CCC_WRITE_PROTECTION         (1 << 6)
#define SD_CSD_CCC_LOCK_CARD                (1 << 7)
#define SD_CSD_CCC_APPLICATION_SPECIFIC     (1 << 8)
#define SD_CSD_CCC_RESERVED9                (1 << 9)
#define SD_CSD_CCC_RESERVED10               (1 << 10)
#define SD_CSD_CCC_RESERVED11               (1 << 11)

// CSD definitions for MMC cards
#define MMC_CSD_ER_GRP_SIZE_BIT_SLICE       42
#define MMC_CSD_ER_GRP_SIZE_SLICE_SIZE      5
#define MMC_CSD_ER_GRP_MULT_BIT_SLICE       37
#define MMC_CSD_ER_GRP_MULT_SLICE_SIZE      5
#define MMC_CSD_WP_GROUP_SIZE_BIT_SLICE     32
#define MMC_CSD_WP_GROUP_SIZE_SLICE_SIZE    5

#ifdef _MMC_SPEC_42_
// Date : 07.05.14
// Developer : HS.JANG
// Description : It is needed when sends CMD 8
#define MMC_EXTCSD_REGISTER_SIZE    512  // total byte length of Extended CSD register 
#endif

// macros for bit shifting and masking in the CSD register
#define SD_CSD_TRANS_SPEED_VALUE_SHIFT      3
#define SD_CSD_TRANS_SPEED_VALUE_MASK       0x78
#define SD_CSD_TRANS_SPEED_UNIT_MASK        0x07
#define SD_CSD_TAAC_VALUE_MASK              0x78
#define SD_CSD_TAAC_VALUE_SHIFT             3
#define SD_CSD_TAAC_UNIT_MASK               0x07

// SCR register
#define SD_SCR_VERSION_BIT_SLICE            60
#define SD_SCR_VERSION_SLICE_SIZE           4
#define SD_SCR_SD_SPEC_BIT_SLICE            56
#define SD_SCR_SD_SPEC_SLICE_SIZE           4
#define SD_SCR_DATA_STAT_ERASE_BIT_SLICE    55
#define SD_SCR_DATA_STAT_ERASE_SLICE_SIZE   1
#define SD_SCR_SECURITY_SUPPORT_BIT_SLICE   52
#define SD_SCR_SECURITY_SUPPORT_SLICE_SIZE  3
#define SD_SCR_BUS_WIDTH_BIT_SLICE          48
#define SD_SCR_BUS_WIDTH_SLICE_SIZE         4
// bits 0 - 47 reserved   

#define SD_SCR_BUS_WIDTH_1_BIT  0x01    // bit 0
#define SD_SCR_BUS_WIDTH_4_BIT  0x04    // bit 4

#define SD_DSR_REGISTER_SIZE 2

// definitions for IO RW Register and Extended Arguments
#define SD_IO_OP_READ           0   // Read_Write
#define SD_IO_OP_WRITE          1   // Read_Write
#define SD_IO_RW_NORMAL         0   // RAW
#define SD_IO_RW_RAW            1   // RAW
#define SD_IO_BYTE_MODE         0   // BlockMode
#define SD_IO_BLOCK_MODE        1   // BlockMode
#define SD_IO_FIXED_ADDRESS     0   // IncrementAddress
#define SD_IO_INCREMENT_ADDRESS 1   // IncrementAddress

// macro to build RW_Direct Argument
//    Read_Write = 1 (write) or 0 (read)
//    RAW        = 1 (read after write) or 0 (echo write data)
//    Function   = function number 0-7
//    Address    = register address 0-1FFFF
//    Data       = data to write (set to 0 if read)
#define BUILD_IO_RW_DIRECT_ARG(Read_Write, RAW, Function, Address, Data) \
    (((Read_Write & 1) << 31) | ((Function & 0x7) << 28) | \
    ((RAW & 1) << 27) | ((Address & 0x1FFFF) << 9) | \
    (Data & 0xFF))

// macros to split the RW_Direct argument up again
#define IO_RW_DIRECT_ARG_RW(Arg)    (((Arg)>>31)&1)
#define IO_RW_DIRECT_ARG_RAW(Arg)   (((Arg)>>27)&1)
#define IO_RW_DIRECT_ARG_FUNC(Arg)  ((UCHAR)(((Arg)>>28)&0x7))
#define IO_RW_DIRECT_ARG_ADDR(Arg)  (((Arg)>>9)&0x1FFFF)
#define IO_RW_DIRECT_ARG_DATA(Arg)  ((UCHAR)((Arg)&0xFF))


// macro to build RW Extended
//    Read_Write = 1 (write) or 0 (read)
//    BlockMode  = 1 = Block Mode or 0 = byte mode
//    Function   = function number 0-7
//    Address    = register address 0-1FFFF
//    IncrementAddress = 1 = Card should increment the register address
//                       0 = Card should keep the address register fixed
//    count       = 9 bit Block or Byte Count
#define BUILD_IO_RW_EXTENDED_ARG(Read_Write, BlockMode, Function, Address, IncrementAddress, Count) \
    (((Read_Write & 1) << 31) | ((Function & 0x7) << 28) | \
    ((BlockMode & 1) << 27) | ((IncrementAddress & 1) << 26) | ((Address & 0x1FFFF) << 9) | \
    (Count & 0x1FF))

// macros to split the RW_Extended argument up again
#define IO_RW_EXTENDED_ARG_RW(Arg)      IO_RW_DIRECT_ARG_RW(Arg)
#define IO_RW_EXTENDED_ARG_BLK(Arg)     (((Arg)>>27)&1)
#define IO_RW_EXTENDED_ARG_OP(Arg)      (((Arg)>>26)&1)
#define IO_RW_EXTENDED_ARG_FUNC(Arg)    IO_RW_DIRECT_ARG_FUNC(Arg)
#define IO_RW_EXTENDED_ARG_ADDR(Arg)    IO_RW_DIRECT_ARG_ADDR(Arg) 
#define IO_RW_EXTENDED_ARG_CNT(Arg)     ((Arg)&0x1FF)


#define SDIO_CCCR_SPEC_REV_MASK     0x0F
#define SDIO_CCCR_SPEC_REV_1_0      0x00
#define SDIO_CCCR_SPEC_REV_1_1      0x01
// SDIO register offsets in the Common Register Area
#define SD_IO_REG_CCCR              0x00
#define SD_IO_REG_SPEC_REV          0x01
#define SD_IO_REG_ENABLE            0x02
#define SD_IO_REG_IO_READY          0x03
#define SD_IO_REG_INT_ENABLE        0x04
#define SD_IO_REG_INT_PENDING       0x05
#define SD_IO_REG_IO_ABORT          0x06
#define SD_IO_REG_BUS_CONTROL       0x07
#define SD_IO_REG_CARD_CAPABILITY   0x08
#define SD_IO_REG_COMMON_CIS_POINTER 0x09   // extends to 0xA, 0xB for 24 bits total 
#define SD_IO_REG_BUS_SUSPEND        0x0C
#define SD_IO_REG_FUNCTION_SELECT    0x0D
#define SD_IO_REG_EXEC_FLAGS         0x0E
#define SD_IO_REG_READY_FLAGS        0x0F
#define SD_IO_REG_FB0_BLOCK_SIZE     0x10   // extends to 0x11, for 16 bits total
#define SD_IO_REG_POWER_CONTROL      0x12   // Power Control

#define SD_IO_CIS_PTR_BYTES          3
#define SD_IO_CSA_PTR_BYTES          3

// FBR Definitions
#define SD_IO_FBR_1_OFFSET           0x100  // Function Basic Information Register offset
#define SD_IO_FBR_DEVICE_CODE        0x0    // Device code offset from FBR base
#define SD_IO_FBR_DEVICE_CODE_EXT    0x1    // Device code extention offset (1.1 only devices)
#define SD_IO_FBR_POWER_SELECT       0x2    // Power Control offset (1.1 only devices)
#define SD_IO_FBR_CISP_BYTE_0        0x9    // CIS Pointer byte 0 offset from FBR base
#define SD_IO_FBR_CISP_BYTE_1        0xA    // CIS Pointer byte 1 offset from FBR base
#define SD_IO_FBR_CISP_BYTE_2        0xB    // CIS Pointer byte 2 offset from FBR base
#define SD_IO_FBR_CSAP_BYTE_0        0xC    // CSA pointer byte 0 offerst from FBR
#define SD_IO_FBR_CSAP_BYTE_1        0xD    // CSA pointer byte 1 offerst from FBR
#define SD_IO_FBR_CSAP_BYTE_2        0xE    // CSA pointer byte 2 offerst from FBR
#define SD_IO_FBR_DATA_ACCESS        0xF    // CSA data access offset
#define SD_IO_FBR_IO_BLOCK_SIZE      0x10   // I/O block size, spans 2 bytes
#define SD_IO_FBR_LENGTH             0x100  // FBR register length

// I/O Abort register Bit definitions
#define SD_IO_REG_IO_ABORT_RES       (1 << 3)
#define SD_IO_REG_IO_ABORT_AS2       (1 << 2)
#define SD_IO_REG_IO_ABORT_AS1       (1 << 1)
#define SD_IO_REG_IO_ABORT_AS0       (1 << 0)

// Card Capability Bit definitions
#define SD_IO_CARD_CAP_4_BIT_LOW_SPEED             (1 << 7)
#define SD_IO_CARD_CAP_LOW_SPEED                   (1 << 6)
#define SD_IO_CARD_CAP_ENABLE_INTS_4_BIT_MB_MODE   (1 << 5)
#define SD_IO_CARD_CAP_SUPPORTS_INTS_4_BIT_MB_MODE (1 << 4)
#define SD_IO_CARD_CAP_SUPPORTS_SUSPEND_RESUME     (1 << 3)
#define SD_IO_CARD_CAP_SUPPORTS_READ_WAIT          (1 << 2)
#define SD_IO_CARD_CAP_SUPPORTS_MULTI_BLOCK_TRANS  (1 << 1)
#define SD_IO_CARD_CAP_SUPPORTS_DIRECT_COMMAND     (1 << 0)

#define SD_IO_CARD_POWER_CONTROL_SUPPORT        (1 << 0)
#define SD_IO_CARD_POWER_CONTROL_ENABLE         (1 << 1)

#define SD_IO_FUNCTION_POWER_SELECT_SUPPORT    (1 << 0)
#define SD_IO_FUNCTION_POWER_SELECT_STATE      (1 << 1)

#define SD_MASK_FOR_33V_POWER_CONTROL_TUPLE     0x00FF8000      // 3.6 V to 2.7 Volts


// device code mask 
#define SDIO_DEV_CODE_MASK           0x0F
// device I/O extension token
#define SDIO_DEV_CODE_USES_EXTENSION 0x0F

// bit definitions for BUS CONTROL registers
#define SD_IO_BUS_CONTROL_CD_DETECT_DISABLE        (1 << 7)
#define SD_IO_BUS_CONTROL_BUS_WIDTH_1BIT           0x00
#define SD_IO_BUS_CONTROL_BUS_WIDTH_4BIT           0x02

// bit definition for Interrupt enable register
#define SD_IO_INT_ENABLE_MASTER_ENABLE       (1 << 0)
#define SD_IO_INT_ENABLE_ALL_FUNCTIONS       0xFE

// response flag bits
#define SD_IO_R5_RESPONSE_FLAGS_BYTE_OFFSET  0x02
#define SD_IO_R5_RESPONSE_DATA_BYTE_OFFSET   0x01

#define SD_IO_R5_RESPONSE_ERROR_MASK         0xCB  // bits 7,6,3,1,0
#define SD_IO_COM_CRC_ERROR                  0x80
#define SD_IO_ILLEGAL_COMMAND                0x40
#define SD_IO_GENERAL_ERROR                  0x08
#define SD_IO_INVALID_FUNCTION               0x02
#define SD_IO_ARG_OUT_OF_RANGE               0x01

#define SD_IO_R5_RESPONSE_ERROR(r)  ((r) & SD_IO_R5_RESPONSE_ERROR_MASK)

#define SDCARD_COMMAND_BUFFER_BYTES     6           // 48 bit commands
#define SDCARD_RESPONSE_BUFFER_BYTES    17          // max 136 bits
#define SD_DEFAULT_CARD_ID_CLOCK_RATE   100000      // 100 khz 
#define SD_LOW_SPEED_RATE               400000      // 400 khz
#define SD_FULL_SPEED_RATE              25000000    // 25 Mhz
#define SDHC_FULL_SPEED_RATE           	50000000    // 52 Mhz
#define MMC_FULL_SPEED_RATE             20000000    // 20 Mhz
#define MMCPLUS_SPEED_RATE      				26000000	  // 26 Mhz
#define HSMMC_FULL_SPEED_RATE         	52000000    // 52 Mhz

#endif _SDCARD_H_

// DO NOT REMOVE --- END EXTERNALLY DEVELOPED SOURCE CODE ID --- DO NOT REMOVE