xpseudo_asm_gcc.h

xilinx内嵌CPU下的UCOS移植

/* $Id: xpseudo_asm_gcc.h,v 1.11.2.1 2008/02/29 21:12:04 meinelte Exp $ */
/******************************************************************************
*
*       XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
*       AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
*       SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,
*       OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
*       APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
*       THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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*       FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
*       WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
*       IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
*       REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
*       INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
*       FOR A PARTICULAR PURPOSE.
*
*       (c) Copyright 2007 Xilinx Inc.
*       All rights reserved.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm_gcc.h
*
* This header file contains macros for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver   Who  Date      Changes
* ----- ---- --------  -----------------------------------------------
* 1.00a ch   06/18/02  First release
* 1.01  mdb  2005/7/29 Added tlbsx. command
* 1.02  mdb  2005/8/15 Added tlbre, mfcr commands
* 1.02a ecm  04/06/07  moved over from standalone bsp and updated to standards
* 1.02a ecm  02/29/08  uncommented the user defined instructions, supported by
*			 		   gcc now.
* </pre>
*
******************************************************************************/

#ifndef XPSEUDO_ASM_H  /* prevent circular inclusions */
#define XPSEUDO_ASM_H  /* by using protection macros */

#ifdef __cplusplus
extern "C" {
#endif

/***************************** Include Files ********************************/
#ifndef XENV_VXWORKS
#include <ppc-asm.h>
#endif
#include "xreg440.h"
#define r2 2
#define r1 1

/************************** Constant Definitions ****************************/

/**************************** Type Definitions ******************************/

/***************** Macros (Inline Functions) Definitions ********************/

/* necessary for pre-processor */
#define stringify(s)    tostring(s)
#define tostring(s)     #s

/* pseudo assembler instructions */

#define mtgpr(rn, v)    __asm__ __volatile__(\
                          "mr " stringify(rn) ",%0\n"\
                          : : "r" (v)\
                        )

#define mfgpr(rn)       ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "mr %0," stringify(rn) "\n"\
                            : "=r" (rval)\
                          );\
                          rval;\
                        })

#define mtspr(rn, v)    __asm__ __volatile__(\
                          "mtspr " stringify(rn) ",%0\n"\
                          : : "r" (v)\
                        )

#define mfspr(rn)       ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "mfspr %0," stringify(rn) "\n"\
                            : "=r" (rval)\
                          );\
                          rval;\
                        })

#define mtdcr(rn, v)    __asm__ __volatile__(\
                          "mtdcr " stringify(rn) ",%0\n"\
                          : : "r" (v)\
                        )

#define mfdcr(rn)       ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "mfdcr %0," stringify(rn) "\n"\
                            : "=r" (rval)\
                          );\
                          rval;\
                        })

#define mtmsr(v)        __asm__ __volatile__(\
                          "mtmsr %0\n"\
                          : : "r" (v)\
                        )

#define mfmsr()         ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "mfmsr %0\n"\
                            : "=r" (rval)\
                          );\
                          rval;\
                        })

#define mfcr()          ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "mfcr %0\n"\
                            : "=r" (rval)\
                          );\
                          rval;\
                        })

#define mtivpr(adr)     mtspr(XREG_SPR_IVPR, (adr))
#define mtivor0(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR0) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor1(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR1) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor2(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR2) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor3(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR3) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor4(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR4) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor5(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR5) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor6(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR6) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor7(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR7) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor8(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR8) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor9(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR9) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor10(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR10) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor11(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR11) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor12(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR12) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor13(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR13) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor14(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR14) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtivor15(v)      __asm__ __volatile__(\
                          "mtspr " stringify(XREG_SPR_IVOR15) ",%0\n"\
                          : : "r" (v)\
                        )
#define mtcsrr0(v)      mtspr(XREG_SPR_CSRR0, (v))
#define mtcsrr1(v)      mtspr(XREG_SPR_CSRR1, (v))
#define mtmcsrr0(v)     mtspr(XREG_SPR_MCSRR0, (v))
#define mtmcsrr1(v)     mtspr(XREG_SPR_MCSRR1, (v))

/************************* instruction cache operations ***********************/
#define icbi(adr)       __asm__ __volatile__("icbi  %0,%1\n" : : "r" (0), "r" (adr))
#define icbt(adr)       __asm__ __volatile__("icbt  %0,%1\n" : : "r" (0), "r" (adr))
/* no arguments needed but retained for compatibilty with the PPC405 */
#define iccci           __asm__ __volatile__("iccci 0,0\n")
#define icread(adr)     __asm__ __volatile__("icread %0,%1\n" : : "r" (0), "r" (adr))

/***************************** data cache operations **************************/
#define dcbf(adr)       __asm__ __volatile__("dcbf  %0,%1\n" : : "r" (0), "r" (adr))
#define dcbi(adr)       __asm__ __volatile__("dcbi  %0,%1\n" : : "r" (0), "r" (adr))
#define dcbst(adr)      __asm__ __volatile__("dcbst %0,%1\n" : : "r" (0), "r" (adr))
#define dcbt(adr)       __asm__ __volatile__("dcbt  %0,%1\n" : : "r" (0), "r" (adr))
#define dcbz(adr)       __asm__ __volatile__("dcbz  %0,%1\n" : : "r" (0), "r" (adr))
/* no arguments needed but retained for compatibilty with the PPC405 */
#define dccci(adr)      __asm__ __volatile__("dccci 0,%0\n" : : "r" (adr))
#define dcread(adr)     ({register unsigned int rval; \
                          __asm__ __volatile__("\
                            dcread %0,%1,%2\n"\
                            : "=r" (rval) : "r" (0), "r" (adr)\
                          );\
                          rval;\
                        })

/*************************** synchonrization operations ***********************/
#define isync           __asm__ __volatile__("isync\n")
/*
 * 'sync' instruction will break vxworks BSP build, however standalone BSP
 * is using this instruction. Have to use this conditional statement make both
 * happy.
 */
#if !defined(XENV_VXWORKS)
#define sync            __asm__ __volatile__("sync\n")
#endif
#define msync           __asm__ __volatile__("msync\n")
#define mbar            __asm__ __volatile__("mbar\n")
#define eieio           __asm__ __volatile__("eieio\n")

#define tlbsx(adr, offset)        ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "tlbsx. %0,%1,%2\n" \
                            : "=r" (rval) \
                            : "r" (adr), "r" (offset) \
                          );\
                          rval; })

#define tlbre(entry, word)        ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "tlbre %0,%1,%2\n" \
                            : "=r" (rval) \
                            : "r" (entry), "i" (word) \
                          );\
                          rval; })

#define tlbwe(val, index, word) __asm__ __volatile__(\
                            "tlbwe %0,%1,%2\n" \
                            : : "r"(val), "r"(index), "i"(word) \
                         )

#define lbz(adr)        ({unsigned char rval; \
                          __asm__ __volatile__(\
                            "lbz %0,0(%1)\n"\
                            : "=r" (rval) : "b" (adr)\
                          );\
                          rval;\
                        })

#define lhz(adr)        ({unsigned short rval; \
                          __asm__ __volatile__(\
                            "lhz %0,0(%1)\n"\
                            : "=r" (rval) : "b" (adr)\
                          );\
                          rval;\
                        })

#define lwz(adr)        ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "lwz %0,0(%1)\n"\
                            : "=r" (rval) : "b" (adr)\
                          );\
                          rval;\
                        })

#define stb(adr, val)   __asm__ __volatile__(\
                          "stb %0,0(%1)\n"\
                          : : "r" (val), "b" (adr)\
                        )

#define sth(adr, val)   __asm__ __volatile__(\
                          "sth %0,0(%1)\n"\
                          : : "r" (val), "b" (adr)\
                        )

#define stw(adr, val)   __asm__ __volatile__(\
                          "stw %0,0(%1)\n"\
                          : : "r" (val), "b" (adr)\
                        )

#define lhbrx(adr)      ({unsigned short rval; \
                          __asm__ __volatile__(\
                            "lhbrx %0,0,%1\n"\
                            : "=r" (rval) : "r" (adr)\
                          );\
                          rval;\
                        })

#define lwbrx(adr)      ({unsigned int rval; \
                          __asm__ __volatile__(\
                            "lwbrx %0,0,%1\n"\
                            : "=r" (rval) : "r" (adr)\
                          );\
                          rval;\
                        })

#define sthbrx(adr, val)  __asm__ __volatile__(\
                            "sthbrx %0,0,%1\n"\
                            : : "r" (val), "r" (adr)\
                          )

#define stwbrx(adr, val)  __asm__ __volatile__(\
                            "stwbrx %0,0,%1\n"\
                            : : "r" (val), "r" (adr)\
                          )

#define wrtee(v)        __asm__ __volatile__(\
                          "wrtee %0\n"\
                          : : "r" (v)\
                        )

#define wrteei(v)        __asm__ __volatile__(\
                          "wrteei " stringify(v) "\n"\
                        )


/* Blocking Data Read and Write to FSL no. id */
#define getfsl(val, id)         __asm__ __volatile__ (\
                                        "get %0, " #id : "=r" (val))

#define putfsl(val, id)         __asm__ __volatile__(\
                                        "put %0, " #id :: "r" (val))

/* Non-blocking Data Read and Write to FSL no. id */
#define ngetfsl(val, id)        __asm__ __volatile__(\
                                        "nget %0, " #id : "=r" (val))

#define nputfsl(val, id)        __asm__ __volatile__(\
                                        "nput %0, " #id :: "r" (val))

/* Blocking Control Read and Write to FSL no. id */
#define cgetfsl(val, id)        __asm__ __volatile__(\
                                        "cget %0, " #id : "=r" (val))

#define cputfsl(val, id)        __asm__ __volatile__(\
                                        "cput %0, " #id :: "r" (val))


/* Non-blocking Control Read and Write to FSL no. id */
#define ncgetfsl(val, id)       __asm__ __volatile__(\
                                        "ncget %0, " #id : "=r" (val))

#define ncputfsl(val, id)       __asm__ __volatile__(\
                                        "ncput %0, " #id :: "r" (val))



/************************** APU UDI FCM Level 2 Internal Macros ****************************/

/************************** udi<n>fcm. Instruction Combinations ****************************/

/* udi0fcm. */

#define UDI0FCMCR_GPR_GPR_GPR(a, b, c)                    \
        __asm__ __volatile__("udi0fcm. %0,%1,%2" : "=r"(a) :  "r"(b), "r"(c))

#define UDI0FCMCR_GPR_GPR_IMM(a, b, c)                    \
        __asm__ __volatile__("udi0fcm. %0,%1," #c : "=r"(a) :  "r"(b))

#define UDI0FCMCR_GPR_IMM_IMM(a, b, c)                    \
        __asm__ __volatile__("udi0fcm. %0," #b "," #c : "=r"(a))