system_shapes.xml

microblaze下ucos移植源码

      <PORT DIR="O" MPD_INDEX="50" NAME="PLB_MRdErr" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="51" NAME="PLB_MWrErr" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="52" NAME="PLB_MRdBTerm" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="53" NAME="PLB_MRdDAck" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="54" NAME="PLB_MRdDBus" SIGNAME="__DEF__" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/>
      <PORT DIR="O" MPD_INDEX="55" NAME="PLB_MRdWdAddr" SIGNAME="__DEF__" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/>
      <PORT DIR="O" MPD_INDEX="56" NAME="PLB_MRearbitrate" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="57" NAME="PLB_MWrBTerm" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="58" NAME="PLB_MWrDAck" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="59" NAME="PLB_MSSize" SIGNAME="__DEF__" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/>
      <PORT DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="65" NAME="PLB_TAttribute" SIGNAME="__DEF__" VECFORMULA="[0:15]"/>
      <PORT DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="67" NAME="PLB_masterID" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="68" NAME="PLB_MSize" SIGNAME="__DEF__" VECFORMULA="[0:1]"/>
      <PORT DIR="O" MPD_INDEX="69" NAME="PLB_rdPendPri" SIGNAME="__DEF__" VECFORMULA="[0:1]"/>
      <PORT DIR="O" MPD_INDEX="70" NAME="PLB_wrPendPri" SIGNAME="__DEF__" VECFORMULA="[0:1]"/>
      <PORT DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="74" NAME="PLB_rdPrim" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
      <PORT DIR="O" MPD_INDEX="75" NAME="PLB_reqPri" SIGNAME="__DEF__" VECFORMULA="[0:1]"/>
      <PORT DIR="O" MPD_INDEX="76" NAME="PLB_size" SIGNAME="__DEF__" VECFORMULA="[0:3]"/>
      <PORT DIR="O" MPD_INDEX="77" NAME="PLB_type" SIGNAME="__DEF__" VECFORMULA="[0:2]"/>
      <PORT DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="79" NAME="PLB_wrDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="80" NAME="PLB_wrPrim" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
      <PORT DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="82" NAME="PLB_SMRdErr" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="83" NAME="PLB_SMWrErr" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="84" NAME="PLB_SMBusy" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
      <PORT DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="88" NAME="PLB_SrdDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="89" NAME="PLB_SrdWdAddr" SIGNAME="__DEF__" VECFORMULA="[0:3]"/>
      <PORT DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="91" NAME="PLB_Sssize" SIGNAME="__DEF__" VECFORMULA="[0:1]"/>
      <PORT DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      <BUSINTERFACE BIFRANK="SLAVE" BUSNAME="__NOC__" BUSSTD="DCR" BUS_STD="DCR" MPD_INDEX="0" NAME="SDCR"/>
      <MEMORYMAP>
        <MEMRANGE BASE="0b1111111111" BASENAME="C_BASEADDR" BASEVALUE="1023" HIGH="0b0000000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0" SIZE="0" SIZEABRV="U">
          <MEMBUSINTERFACES>
            <MEMBUSINTERFACE NAME="SDCR"/>
          </MEMBUSINTERFACES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="LMB" BUS_STD="LMB" DOC_IP="c:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" HWVERSION="1.00.a" INSTANCE="ilmb" IPTYPE="BUS" IS_PLACED="TRUE" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="lmb_v10" SAV_INDEX="2">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <PARAMETER MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" VALUE="4"/>
      <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" VALUE="32"/>
      <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" VALUE="32"/>
      <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
      <PORT DIR="I" INMHS="TRUE" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
      <PORT DIR="I" INMHS="TRUE" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/>
      <PORT DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="3" NAME="M_ABus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="7" NAME="M_DBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="8" NAME="M_BE" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
      <PORT DIR="I" MPD_INDEX="9" NAME="Sl_DBus" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
      <PORT DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
      <PORT DIR="O" MPD_INDEX="11" NAME="LMB_ABus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="15" NAME="LMB_ReadDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="16" NAME="LMB_WriteDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="18" NAME="LMB_BE" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
    </MODULE>
    <MODULE BUSSTD="LMB" BUS_STD="LMB" DOC_IP="c:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" HWVERSION="1.00.a" INSTANCE="dlmb" IPTYPE="BUS" IS_PLACED="TRUE" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10" SAV_INDEX="1">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <PARAMETER MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" VALUE="4"/>
      <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" VALUE="32"/>
      <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" VALUE="32"/>
      <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
      <PORT DIR="I" INMHS="TRUE" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
      <PORT DIR="I" INMHS="TRUE" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/>
      <PORT DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="3" NAME="M_ABus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="7" NAME="M_DBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="8" NAME="M_BE" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
      <PORT DIR="I" MPD_INDEX="9" NAME="Sl_DBus" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
      <PORT DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
      <PORT DIR="O" MPD_INDEX="11" NAME="LMB_ABus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="15" NAME="LMB_ReadDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="16" NAME="LMB_WriteDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="18" NAME="LMB_BE" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
    </MODULE>
    <MODULE DOC_DRIVER="c:/Xilinx/10.1/EDK/sw/XilinxProcessorIPLib/drivers/bram_v1_00_a/doc/html/api/index.html" DOC_IP="c:/Xilinx/10.1/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_a/doc/lmb_bram_if_cntlr.pdf" HWVERSION="2.10.a" INSTANCE="dlmb_cntlr" IPTYPE="PERIPHERAL" IS_PLACED="TRUE" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr" SAV_INDEX="4">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="0" NAME="C_BASEADDR" VALUE="0x00000000"/>
      <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" MPD_INDEX="1" NAME="C_HIGHADDR" VALUE="0x00007fff"/>
      <PARAMETER MPD_INDEX="2" NAME="C_MASK" VALUE="0x00800000"/>
      <PARAMETER MPD_INDEX="3" NAME="C_LMB_AWIDTH" VALUE="32"/>
      <PARAMETER MPD_INDEX="4" NAME="C_LMB_DWIDTH" VALUE="32"/>
      <PORT DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="2" NAME="LMB_ABus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="3" NAME="LMB_WriteDBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="__DEF__"/>
      <PORT DIR="I" MPD_INDEX="7" NAME="LMB_BE" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
      <PORT DIR="O" MPD_INDEX="8" NAME="Sl_DBus" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="10" NAME="BRAM_Rst_A" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="11" NAME="BRAM_Clk_A" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="12" NAME="BRAM_EN_A" SIGNAME="__DEF__"/>
      <PORT DIR="O" MPD_INDEX="13" NAME="BRAM_WEN_A" SIGNAME="__DEF__" VECFORMULA="[0:(C_LMB_DWIDTH/8)-1]"/>
      <PORT DIR="O" MPD_INDEX="14" NAME="BRAM_Addr_A" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
      <PORT DIR="I" MPD_INDEX="15" NAME="BRAM_Din_A" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <PORT DIR="O" MPD_INDEX="16" NAME="BRAM_Dout_A" SIGNAME="__DEF__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      <BUSINTERFACE BIFRANK="SLAVE" BIF_X="0" BIF_Y="0" BUSNAME="dlmb" BUSSTD="LMB" BUS_STD="LMB" MPD_INDEX="0" NAME="SLMB"/>
      <BUSINTERFACE BIFRANK="INITIATOR" BIF_X="1" BIF_Y="0" BUSNAME="dlmb_port" BUSSTD="XIL" BUS_STD="XIL_BRAM" IS_INTCONN="TRUE" MPD_INDEX="1" NAME="BRAM_PORT"/>
      <MEMORYMAP>
        <MEMRANGE BASE="0x00000000" BASENAME="C_BASEADDR" BASEVALUE="0" HIGH="0x00007