system.log

microblaze下ucos移植源码

PMSPEC -- Overriding Xilinx file <c:/Xilinx/10.1/EDK/virtex4/data/virtex4.acd>
with local file <c:/Xilinx/10.1/ISE/virtex4/data/virtex4.acd>
Loading device for application Rf_Device from file '4vfx12.nph' in environment
c:\Xilinx\10.1\ISE;c:\Xilinx\10.1\EDK.

   "system" is an NCD, version 3.2, device xc4vfx12, package ff668, speed -10

--------------------------------------------------------------------------------
Release 10.1 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

trce -e 3 -xml system.twx system.ncd system.pcf


Design file:              system.ncd
Physical constraint file: system.pcf
Device,speed:             xc4vfx12,-10 (PRODUCTION 1.68 2008-01-09, STEPPING
level 0)
Report level:             error report
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
   50 Ohm transmission line loading model.  For the details of this model, and
   for more information on accounting for different loading conditions, please
   see the device datasheet.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 431626 paths, 1 nets, and 19696 connections

Design statistics:
   Minimum period:   9.803ns (Maximum frequency: 102.010MHz)
   Maximum net skew:   0.841ns


Analysis completed Thu Aug 07 12:46:48 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Number of info messages: 2
Total time: 14 secs 


xflow done!

touch __xps/system_routed
xilperl c:/Xilinx/10.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par
*********************************************
Running Bitgen..
*********************************************

cd implementation; bitgen -w -f bitgen.ut system

Release 10.1 - Bitgen K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <c:/Xilinx/10.1/EDK/virtex4/data/virtex4.acd>
with local file <c:/Xilinx/10.1/ISE/virtex4/data/virtex4.acd>

Loading device for application Rf_Device from file '4vfx12.nph' in environment
c:\Xilinx\10.1\ISE;c:\Xilinx\10.1\EDK.

   "system" is an NCD, version 3.2, device xc4vfx12, package ff668, speed -10

Opened constraints file system.pcf.

Thu Aug 07 12:46:54 2008

Running DRC.

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/CLKOUT is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<1> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<2> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<3> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<4> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<5> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
   DCM_INST/Using_DCM_ADV.DCM_ADV_INST/clock_generator_0/clock_generator_0/Using
   _DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST/cd/CLK<6> is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
DRC detected 0 errors and 7 warnings.  Please see the previously displayed
individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

cp -f /cygdrive/c/Xilinx/10.1/EDK/sw/lib/microblaze/mb_bootloop.elf bootloops/microblaze_0.elf
*********************************************

Initializing BRAM contents of the bitstream
*********************************************
bitinit system.mhs  -pe microblaze_0  bootloops/microblaze_0.elf  \
-bt implementation/system.bit -o implementation/download.bit


bitinit version Xilinx EDK 10.1.01 Build EDK_K_SP1.3
Copyright (c) Xilinx Inc. 2002.

Parsing MHS File system.mhs...


Overriding IP level properties ...
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 164 - tcl is overriding PARAMETER C_ADDR_TAG_BITS
   value to 0
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 173 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG
   value to 0

Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0
  (0000000000-0x00007fff) dlmb_cntlr	dlmb
  (0000000000-0x00007fff) ilmb_cntlr	ilmb
  (0x81400000-0x8140ffff) LEDs_4Bit	mb_plb
  (0x81420000-0x8142ffff) LEDs_Positions	mb_plb
  (0x81800000-0x8180ffff) xps_intc_0	mb_plb
  (0x83c00000-0x83c0ffff) xps_timer_1	mb_plb
  (0x84000000-0x8400ffff) RS232_Uart	mb_plb
  (0x84100000-0x841fffff) SRAM	mb_plb
  (0x84400000-0x8440ffff) debug_module	mb_plb

Initializing Memory...
Checking ELFs associated with MICROBLAZE instance microblaze_0 for overlap...


Analyzing file bootloops/microblaze_0.elf...
Running Data2Mem with the following command:
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
"bootloops/microblaze_0.elf" tag microblaze_0  -o b implementation/download.bit 

Memory Initialization completed successfully.




Done!

At Local date and time: Thu Aug 07 13:37:10 2008
 make -f system.make EX1_OS_program started...

*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc4vfx12ff668-10   system.mss

libgen
Xilinx EDK 10.1.01 Build EDK_K_SP1.3
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.


Command Line: libgen -mhs system.mhs -p xc4vfx12ff668-10 system.mss 


Output Directory (-od)		:
C:\work_dir\xilinx\AN1013-uCOS-II-MicroBlaze\uCOS-II_and_uBlaze_EDK_10_1_01\
Part (-p)			: virtex4

Software Specification file	: system.mss


Overriding IP level properties ...

INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 164 - tcl is overriding PARAMETER C_ADDR_TAG_BITS
   value to 0
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 173 - tcl is overriding PARAMETER C_DCACHE_ADDR_TAG
   value to 0


Performing IP level DRCs on properties...

Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...
Address Map for Processor microblaze_0
  (0000000000-0x00007fff) dlmb_cntlr	dlmb
  (0000000000-0x00007fff) ilmb_cntlr	ilmb
  (0x81400000-0x8140ffff) LEDs_4Bit	mb_plb
  (0x81420000-0x8142ffff) LEDs_Positions	mb_plb
  (0x81800000-0x8180ffff) xps_intc_0	mb_plb
  (0x83c00000-0x83c0ffff) xps_timer_1	mb_plb
  (0x84000000-0x8400ffff) RS232_Uart	mb_plb
  (0x84100000-0x841fffff) SRAM	mb_plb
  (0x84400000-0x8440ffff) debug_module	mb_plb

Check platform address map ...

Computing clock values...

Overriding system level properties ...
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 125 - tcl is overriding PARAMETER C_D_PLB value to 1
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 126 - tcl is overriding PARAMETER C_D_OPB value to 0
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 128 - tcl is overriding PARAMETER C_I_PLB value to 1
INFO:MDT - IPNAME:microblaze_0 INSTANCE:microblaze -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_b\data\mic
   roblaze_v2_1_0.mpd line 129 - tcl is overriding PARAMETER C_I_OPB value to 0
INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_02_a\data\plb_v4
   6_v2_1_0.mpd line 35 - tool is overriding PARAMETER C_PLBV46_NUM_MASTERS
   value to 2
INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_02_a\data\plb_v4
   6_v2_1_0.mpd line 36 - tool is overriding PARAMETER C_PLBV46_NUM_SLAVES value
   to 7
INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_02_a\data\plb_v4
   6_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_PLBV46_MID_WIDTH value
   to 1
INFO:MDT - IPNAME:mb_plb INSTANCE:plb_v46 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_02_a\data\plb_v4
   6_v2_1_0.mpd line 39 - tool is overriding PARAMETER C_PLBV46_DWIDTH value to
   32
INFO:MDT - IPNAME:ilmb INSTANCE:lmb_v10 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v1
   0_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to
   1
INFO:MDT - IPNAME:dlmb INSTANCE:lmb_v10 -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v1_00_a\data\lmb_v1
   0_v2_1_0.mpd line 37 - tool is overriding PARAMETER C_LMB_NUM_SLAVES value to
   1

INFO:MDT - IPNAME:dlmb_cntlr INSTANCE:lmb_bram_if_cntlr -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\d
   ata\lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK
   value to 0x80000000
INFO:MDT - IPNAME:ilmb_cntlr INSTANCE:lmb_bram_if_cntlr -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v2_10_a\d
   ata\lmb_bram_if_cntlr_v2_1_0.mpd line 43 - tcl is overriding PARAMETER C_MASK
   value to 0x80000000
INFO:MDT - IPNAME:lmb_bram INSTANCE:bram_block -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bra
   m_block_v2_1_0.mpd line 36 - tool is overriding PARAMETER C_MEMSIZE value to
   0x8000
INFO:MDT - IPNAME:RS232_Uart INSTANCE:xps_uartlite -
   c:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_00_a\data\x