📄 system.log
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Logic has been added to automatically put the DCMs in auto-calibration
mode if the clock input or clock feedback ever stops. This is recommended
to ensure that the DCMs will maintain maximum operating frequency for the
following Virtex-4 devices: Production Step 2 for LX/SX, and all Productions
for FX. The extra logic insertion can be disabled by placing the
DCM_AUTOCALIBRATION=FALSE attribute on each applicable DCM or by setting
the environment variable XIL_DCM_AUTOCALIBRATION_OFF. For more information
regarding the DCM auto-calibration mode, please consult Answer Record 21435.
Mapping completed.
See MAP report file "system_map.mrp" for details.
#----------------------------------------------#
# Starting program par
# par -w -ol high system_map.ncd system.ncd system.pcf
#----------------------------------------------#
Release 10.1 - par K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
PMSPEC -- Overriding Xilinx file <c:/Xilinx/10.1/EDK/data/parBmgr.acd> with local file
<c:/Xilinx/10.1/ISE/data/parBmgr.acd>
Constraints file: system.pcf.
Loading device for application Rf_Device from file '4vfx12.nph' in environment c:\Xilinx\10.1\ISE;c:\Xilinx\10.1\EDK.
"system" is an NCD, version 3.2, device xc4vfx12, package ff668, speed -10
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.68 2008-01-09".
Device Utilization Summary:
Number of BSCANs 1 out of 4 25%
Number of BUFGs 2 out of 32 6%
Number of DCM_ADVs 1 out of 4 25%
Number of DSP48s 3 out of 32 9%
Number of ILOGICs 33 out of 320 10%
Number of External IOBs 75 out of 320 23%
Number of LOCed IOBs 75 out of 75 100%
Number of OLOGICs 70 out of 320 21%
Number of RAMB16s 16 out of 36 44%
Number of Slices 2932 out of 5472 53%
Number of SLICEMs 305 out of 2736 11%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
Starting Router
Phase 1: 21405 unrouted; REAL time: 11 secs
Phase 2: 18069 unrouted; REAL time: 12 secs
Phase 3: 5713 unrouted; REAL time: 16 secs
Phase 4: 5713 unrouted; (56187) REAL time: 16 secs
Phase 5: 5730 unrouted; (3817) REAL time: 19 secs
Phase 6: 5732 unrouted; (0) REAL time: 19 secs
Phase 7: 0 unrouted; (0) REAL time: 26 secs
Phase 8: 0 unrouted; (0) REAL time: 28 secs
Phase 9: 0 unrouted; (0) REAL time: 30 secs
Total REAL time to Router completion: 32 secs
Total CPU time to Router completion: 31 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| dlmb_port_BRAM_Clk | BUFGCTRL_X0Y1| No | 2467 | 0.354 | 2.715 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/Dbg_Clk | | | | | |
| _1 | BUFGCTRL_X0Y0| No | 148 | 0.242 | 2.604 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_pin_IBUFG | Local| | 7 | 0.374 | 1.459 |
+---------------------+--------------+------+------+------------+-------------+
|debug_module/Dbg_Upd | | | | | |
| ate_1 | Local| | 30 | 0.748 | 1.907 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/FASTCLK | Local| | 3 | 0.000 | 0.517 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/CLKOUT | Local| | 6 | 0.381 | 0.867 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV
| | | | | |
| _INST/cd/CLK<1> | Local| | 2 | 0.000 | 0.492 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/cd/CLK<2> | Local| | 2 | 0.000 | 0.463 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/cd/CLK<3> | Local| | 2 | 0.000 | 0.457 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/cd/CLK<4> | Local| | 2 | 0.000 | 0.663 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/cd/CLK<5> | Local| | 2 | 0.000 | 0.485 |
+---------------------+--------------+------+------+------------+-------------+
|DCM_AUTOCALIBRATION_ | | | | | |
|clock_generator_0/cl | | | | | |
|ock_generator_0/Usin | | | | | |
|g_DCM0.DCM0_INST/DCM | | | | | |
|_INST/Using_DCM_ADV. | | | | | |
|DCM_ADV_INST/clock_g | | | | | |
|enerator_0/clock_gen | | | | | |
|erator_0/Using_DCM0. | | | | | |
|DCM0_INST/DCM_INST/U | | | | | |
|sing_DCM_ADV.DCM_ADV | | | | | |
| _INST/cd/CLK<6> | Local| | 2 | 0.000 | 0.462 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
TS_clock_generator_0_clock_generator_0_DC | SETUP | 0.197ns| 9.803ns| 0| 0
M0_CLK_OUT_0_ = PERIOD TIMEGRP "c | HOLD | 0.480ns| | 0| 0
lock_generator_0_clock_generator_0_DCM0_C | | | | |
LK_OUT_0_" TS_sys_clk_pin HIGH 50 | | | | |
% | | | | |
------------------------------------------------------------------------------------------------------
NET "debug_module/Dbg_Update_1" MAXSKEW = | NETSKEW | 1.159ns| 0.841ns| 0| 0
2 ns | | | | |
------------------------------------------------------------------------------------------------------
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP | 8.807ns| 1.193ns| 0| 0
pin" 10 ns HIGH 50% | HOLD | 0.376ns| | 0| 0
------------------------------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 10.000ns| 1.193ns| 9.803ns| 0| 0| 4| 431622|
| TS_clock_generator_0_clock_gen| 10.000ns| 9.803ns| N/A| 0| 0| 431622| 0|
| erator_0_DCM0_CLK_OUT_0_ | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 41 secs
Total CPU time to PAR completion: 37 secs
Peak Memory Usage: 280 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0
Writing design to file system.ncd
PAR done!
#----------------------------------------------#
# Starting program post_par_trce
# trce -e 3 -xml system.twx system.ncd system.pcf
#----------------------------------------------#
Release 10.1 - Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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