system.log

microblaze下ucos移植源码

   TTACHMENT/I_BURST_SUPPORT/CONTROL_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN[
   5].FDRE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'SRAM/SRAM/MCH_PLB_IPIF_I/INCLUDE_PLB_IPIF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_A
   TTACHMENT/I_BURST_SUPPORT/RESPONSE_DBEAT_CNTR_I/STRUCTURAL_A_GEN.I_ADDSUB_GEN
   [5].FDRE_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[20].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[19].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[18].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[17].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[16].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[15].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[14].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[13].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[12].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[11].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[10].TCSR1_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIME
R_CONTROL_I/TCSR1_GENERATE[9].TCSR1_FF
   _I' has unconnected output pin

WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[8].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[7].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[6].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[5].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[4].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[3].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[2].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[1].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[0].TCSR1_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[20].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[19].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[18].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[17].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[16].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[15].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[14].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[13].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[12].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[11].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[10].TCSR0_F
   F_I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[9].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[8].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[7].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[6].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[5].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[4].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[3].TCSR0_FF
   _I' has unco
nnected output pin

WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[2].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[1].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'xps_timer_1/xps_timer_1/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[0].TCSR0_FF
   _I' has unconnected output pin
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
   debug_module/debug_module/BUFG_DRCK1 drives no clock pins

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  54

Writing NGD file "system.ngd" ...

Writing NGDBUILD log file "system.bld"...

NGDBUILD done.



#----------------------------------------------#
# Starting program map
# map -o system_map.ncd -pr b -ol high -timing system.ngd system.pcf 
#----------------------------------------------#

Release 10.1 - Map K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
PMSPEC -- Overriding Xilinx file <c:/Xilinx/10.1/EDK/data/Xdh_PrimTypeLib.xda>
with local file <c:/Xilinx/10.1/ISE/data/Xdh_PrimTypeLib.xda>
Using target part "4vfx12ff668-10".

Mapping design into LUTs...

Writing file system_map.ngm...
Running directed packing...
Running delay-based LUT packing...

Running timing-driven packing...


Phase 1.1
Phase 1.1 (Checksum:9b2ca5) REAL time: 12 secs 


Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 12 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 12 secs 

Phase 4.2



Phase 4.2 (Checksum:26259fc) REAL time: 14 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 14 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 14 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 14 secs 

Phase 8.4

........................................
..........
...............

Phase 8.4 (Checksum:98caa7) REAL time: 24 secs 

Phase 9.28
Phase 9.28 (Checksum:55d4a77) REAL time: 24 secs 

Phase 10.8
.............................
..........
.....................................

..........

.......................
..........................

................

................

...............
....
...............................................

Phase 10.8 (Checksum:e17774) REAL time: 43 secs 

Phase 11.29
Phase 11.29 (Checksum:68e7775) REAL time: 43 secs 

Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 44 secs 

Phase 13.18

Phase 13.18 (Checksum:7bfa473) REAL time: 1 mins 20 secs 

Phase 14.27
Phase 14.27 (Checksum:8583af2) REAL time: 1 mins 21 secs 

Phase 15.5
Phase 15.5 (Checksum:8f0d171) REAL time: 1 mins 21 secs 

Phase 16.34
Phase 16.34 (Checksum:98967f0) REAL time: 1 mins 21 secs 

REAL time consumed by placer: 1 mins 22 secs 
CPU  time consumed by placer: 1 mins 18 secs 


Design Summary:
Number of errors:      0
Number of warnings:   21
Logic Utilization:
  Total Number Slice Registers:       2,683 out of  10,944   24%
    Number used as Flip Flops:        2,682
    Number used as Latches:               1
    Number of Slice FFs used for
    DCM autocalibration logic:          7 out of   2,682    1%
  Number of 4 input LUTs:             3,438 out of  10,944   31%
    Number of LUTs used for
    DCM autocalibration logic:          4 out of   3,438    1%
      *See INFO below for an explanation of the DCM autocalibration logic
       added by Map
Logic Distribution:
  Number of occupied Slices:          2,932 out of   5,472   53%
    Number of Slices containing only related logic:   2,932 out of   2,932 100%
    Number of Slices containing unrelated logic:          0 out of   2,932   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       3,556 out of  10,944   32%
    Number used as logic:             2,873
    Number used as a route-thru:        118
    Number used for Dual Port RAMs:     384
      (Two LUTs used per Dual Port RAM)
    Number used as Shift registers:     181
  Number of bonded IOBs:                 75 out of     320   23%
    IOB Flip Flops:                     135
  Number of BUFG/BUFGCTRLs:               2 out of      32    6%
    Number used as BUFGs:                 2
  Number of FIFO16/RAMB16s:              16 out of      36   44%
    Number used as RAMB16s:              16
  Number of DSP48s:                       3 out of      32    9%
  Number of DCM_ADVs:                     1 out of       4   25%
  Number of BSCAN_VIRTEX4s:               1 out of       4   25%

Peak Memory Usage:  348 MB
Total REAL time to MAP completion:  1 mins 47 secs 
Total CPU time to MAP completion:   1 mins 41 secs 

INFO: