stm32f10x_tim.txt

stm32 ucos 精简移殖版本 不需作任何修改直接便可运行。包含串口 定时器

0004ba  8101              STRH     r1,[r0,#8]
;;;799    }
0004bc  4770              BX       lr
;;;800    
                          ENDP

                  TIM_BDTRStructInit PROC
;;;811      /* Set the default configuration */
;;;812      TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
0004be  2100              MOVS     r1,#0
0004c0  8001              STRH     r1,[r0,#0]
;;;813      TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
0004c2  8041              STRH     r1,[r0,#2]
;;;814      TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
0004c4  8081              STRH     r1,[r0,#4]
;;;815      TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
0004c6  80c1              STRH     r1,[r0,#6]
;;;816      TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
0004c8  8101              STRH     r1,[r0,#8]
;;;817      TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
0004ca  8141              STRH     r1,[r0,#0xa]
;;;818      TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
0004cc  8181              STRH     r1,[r0,#0xc]
;;;819    }
0004ce  4770              BX       lr
;;;820    
                          ENDP

                  TIM_Cmd PROC
;;;835      
;;;836      if (NewState != DISABLE)
0004d0  b121              CBZ      r1,|L1.1244|
;;;837      {
;;;838        /* Enable the TIM Counter */
;;;839        TIMx->CR1 |= CR1_CEN_Set;
0004d2  8801              LDRH     r1,[r0,#0]
0004d4  f041f041          ORR      r1,r1,#1
0004d8  8001              STRH     r1,[r0,#0]
;;;840      }
;;;841      else
;;;842      {
;;;843        /* Disable the TIM Counter */
;;;844        TIMx->CR1 &= CR1_CEN_Reset;
;;;845      }
;;;846    }
0004da  4770              BX       lr
                  |L1.1244|
0004dc  8801              LDRH     r1,[r0,#0]            ;844
0004de  f240f240          MOV      r2,#0x3fe             ;844
0004e2  4011              ANDS     r1,r1,r2              ;844
0004e4  8001              STRH     r1,[r0,#0]            ;844
0004e6  4770              BX       lr
;;;847    
                          ENDP

                  TIM_CtrlPWMOutputs PROC
;;;862    
;;;863      if (NewState != DISABLE)
0004e8  b129              CBZ      r1,|L1.1270|
;;;864      {
;;;865        /* Enable the TIM Main Output */
;;;866        TIMx->BDTR |= BDTR_MOE_Set;
0004ea  f830f830          LDRH     r1,[r0,#0x44]!
0004ee  f441f441          ORR      r1,r1,#0x8000
0004f2  8001              STRH     r1,[r0,#0]
;;;867      }
;;;868      else
;;;869      {
;;;870        /* Disable the TIM Main Output */
;;;871        TIMx->BDTR &= BDTR_MOE_Reset;
;;;872      }  
;;;873    }
0004f4  4770              BX       lr
                  |L1.1270|
0004f6  f830f830          LDRH     r1,[r0,#0x44]!        ;871
0004fa  f3c1f3c1          UBFX     r1,r1,#0,#15          ;871
0004fe  8001              STRH     r1,[r0,#0]            ;871
000500  4770              BX       lr
;;;874    
                          ENDP

                  TIM_ITConfig PROC
;;;902      
;;;903      if (NewState != DISABLE)
000502  b11a              CBZ      r2,|L1.1292|
;;;904      {
;;;905        /* Enable the Interrupt sources */
;;;906        TIMx->DIER |= TIM_IT;
000504  8982              LDRH     r2,[r0,#0xc]
000506  430a              ORRS     r2,r2,r1
000508  8182              STRH     r2,[r0,#0xc]
;;;907      }
;;;908      else
;;;909      {
;;;910        /* Disable the Interrupt sources */
;;;911        TIMx->DIER &= (u16)~TIM_IT;
;;;912      }
;;;913    }
00050a  4770              BX       lr
                  |L1.1292|
00050c  8982              LDRH     r2,[r0,#0xc]          ;911
00050e  438a              BICS     r2,r2,r1              ;911
000510  8182              STRH     r2,[r0,#0xc]          ;911
000512  4770              BX       lr
;;;914    
                          ENDP

                  TIM_GenerateEvent PROC
;;;937      /* Set the event sources */
;;;938      TIMx->EGR = TIM_EventSource;
000514  8281              STRH     r1,[r0,#0x14]
;;;939    }
000516  4770              BX       lr
;;;940    
                          ENDP

                  TIM_DMAConfig PROC
;;;968      /* Set the DMA Base and the DMA Burst Length */
;;;969      TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000518  4311              ORRS     r1,r1,r2
00051a  f8a0f8a0          STRH     r1,[r0,#0x48]
;;;970    }
00051e  4770              BX       lr
;;;971    
                          ENDP

                  TIM_DMACmd PROC
;;;997      
;;;998      if (NewState != DISABLE)
000520  b11a              CBZ      r2,|L1.1322|
;;;999      {
;;;1000       /* Enable the DMA sources */
;;;1001       TIMx->DIER |= TIM_DMASource; 
000522  8982              LDRH     r2,[r0,#0xc]
000524  430a              ORRS     r2,r2,r1
000526  8182              STRH     r2,[r0,#0xc]
;;;1002     }
;;;1003     else
;;;1004     {
;;;1005       /* Disable the DMA sources */
;;;1006       TIMx->DIER &= (u16)~TIM_DMASource;
;;;1007     }
;;;1008   }
000528  4770              BX       lr
                  |L1.1322|
00052a  8982              LDRH     r2,[r0,#0xc]          ;1006
00052c  438a              BICS     r2,r2,r1              ;1006
00052e  8182              STRH     r2,[r0,#0xc]          ;1006
000530  4770              BX       lr
;;;1009   
                          ENDP

                  TIM_InternalClockConfig PROC
;;;1023     /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;1024     TIMx->SMCR &=  SMCR_SMS_Mask;
000532  8901              LDRH     r1,[r0,#8]
000534  f021f021          BIC      r1,r1,#7
000538  8101              STRH     r1,[r0,#8]
;;;1025   }
00053a  4770              BX       lr
;;;1026   /*******************************************************************************
                          ENDP

                  TIM_SelectInputTrigger PROC
;;;1314     /* Get the TIMx SMCR register value */
;;;1315     tmpsmcr = TIMx->SMCR;
00053c  8902              LDRH     r2,[r0,#8]
;;;1316   
;;;1317     /* Reset the TS Bits */
;;;1318     tmpsmcr &= SMCR_TS_Mask;
00053e  f022f022          BIC      r2,r2,#0x70
;;;1319   
;;;1320     /* Set the Input Trigger source */
;;;1321     tmpsmcr |= TIM_InputTriggerSource;
000542  430a              ORRS     r2,r2,r1
;;;1322   
;;;1323     /* Write to TIMx SMCR */
;;;1324     TIMx->SMCR = tmpsmcr;
000544  8102              STRH     r2,[r0,#8]
;;;1325   }
000546  4770              BX       lr
;;;1326   
                          ENDP

                  TIM_ITRxExternalClockConfig PROC
;;;1040   void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
;;;1041   {
000548  b500              PUSH     {lr}
00054a  4603              MOV      r3,r0
;;;1042     /* Check the parameters */
;;;1043     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1044     assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;1045   
;;;1046     /* Select the Internal Trigger */
;;;1047     TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
00054c  4618              MOV      r0,r3
00054e  f7fff7ff          BL       TIM_SelectInputTrigger
;;;1048   
;;;1049     /* Select the External clock mode1 */
;;;1050     TIMx->SMCR |= TIM_SlaveMode_External1;
000552  8918              LDRH     r0,[r3,#8]
000554  f040f040          ORR      r0,r0,#7
000558  8118              STRH     r0,[r3,#8]
;;;1051   }
00055a  bd00              POP      {pc}
;;;1052   /*******************************************************************************
                          ENDP

                  TIM_TIxExternalClockConfig PROC
;;;1072                                   u16 TIM_ICPolarity, u16 ICFilter)
;;;1073   {
00055c  b530              PUSH     {r4,r5,lr}
00055e  460d              MOV      r5,r1
000560  4604              MOV      r4,r0
000562  4611              MOV      r1,r2
;;;1074     /* Check the parameters */
;;;1075     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1076     assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
;;;1077     assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
;;;1078     assert_param(IS_TIM_IC_FILTER(ICFilter));
;;;1079   
;;;1080     /* Configure the Timer Input Clock Source */
;;;1081     if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
000564  2d60              CMP      r5,#0x60
000566  d104              BNE      |L1.1394|
;;;1082     {
;;;1083       TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
000568  2201              MOVS     r2,#1
00056a  4620              MOV      r0,r4
00056c  f7fff7ff          BL       TI2_Config
000570  e003              B        |L1.1402|
                  |L1.1394|
;;;1084     }
;;;1085     else
;;;1086     {
;;;1087       TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
000572  2201              MOVS     r2,#1
000574  4620              MOV      r0,r4
000576  f7fff7ff          BL       TI1_Config
                  |L1.1402|
;;;1088     }
;;;1089   
;;;1090     /* Select the Trigger source */
;;;1091     TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
00057a  4629              MOV      r1,r5
00057c  4620              MOV      r0,r4
00057e  f7fff7ff          BL       TIM_SelectInputTrigger
;;;1092   
;;;1093     /* Select the External clock mode1 */
;;;1094     TIMx->SMCR |= TIM_SlaveMode_External1;
000582  8920              LDRH     r0,[r4,#8]
000584  f040f040          ORR      r0,r0,#7
000588  8120              STRH     r0,[r4,#8]
;;;1095   }
00058a  bd30              POP      {r4,r5,pc}
;;;1096   
                          ENDP

                  TIM_ETRConfig PROC
;;;1204                      u16 ExtTRGFilter)
;;;1205   {
00058c  b510              PUSH     {r4,lr}
;;;1206     u16 tmpsmcr = 0;
;;;1207   
;;;1208     /* Check the parameters */
;;;1209     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1210     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1211     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1212     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1213   
;;;1214     tmpsmcr = TIMx->SMCR;
00058e  8904              LDRH     r4,[r0,#8]
;;;1215   
;;;1216     /* Reset the ETR Bits */
;;;1217     tmpsmcr &= SMCR_ETR_Mask;
000590  b2e4              UXTB     r4,r4
;;;1218   
;;;1219     /* Set the Prescaler, the Filter value and the Polarity */
;;;1220     tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8);
000592  4311              ORRS     r1,r1,r2
000594  ea41ea41          ORR      r1,r1,r3,LSL #8
000598  4321              ORRS     r1,r1,r4
;;;1221   
;;;1222     /* Write to TIMx SMCR */
;;;1223     TIMx->SMCR = tmpsmcr;
00059a  8101              STRH     r1,[r0,#8]
;;;1224   }
00059c  bd10              POP      {r4,pc}
;;;1225   
                          ENDP

                  TIM_ETRClockMode1Config PROC
;;;1118                                u16 ExtTRGFilter)
;;;1119   {
00059e  b510              PUSH     {r4,lr}
0005a0  4604              MOV      r4,r0
;;;1120     u16 tmpsmcr = 0;
;;;1121   
;;;1122     /* Check the parameters */
;;;1123     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1124     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1125     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1126     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1127   
;;;1128     /* Configure the ETR Clock source */
;;;1129     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
0005a2  4620