📄 stm32f10x_tim.txt
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;;;537 tmpccmrx &= CCMR_OC24M_Mask;
000262 f423f423 BIC r5,r3,#0x7000
;;;538
;;;539 /* Select the Output Compare Mode */
;;;540 tmpccmrx |= (u16)(TIM_OCInitStruct->TIM_OCMode << 8);
000266 880b LDRH r3,[r1,#0]
000268 061b LSLS r3,r3,#24
00026a ea45ea45 ORR r3,r5,r3,LSR #16
;;;541
;;;542 /* Reset the Output Polarity level */
;;;543 tmpccer &= CCER_CC4P_Reset;
00026e f424f424 BIC r5,r4,#0x2000
;;;544
;;;545 /* Set the Output Compare Polarity */
;;;546 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OCPolarity << 12);
000272 890c LDRH r4,[r1,#8]
000274 0724 LSLS r4,r4,#28
000276 ea45ea45 ORR r4,r5,r4,LSR #16
;;;547
;;;548 /* Set the Output State */
;;;549 tmpccer |= (u16)(TIM_OCInitStruct->TIM_OutputState << 12);
00027a 884d LDRH r5,[r1,#2]
00027c 072d LSLS r5,r5,#28
00027e ea44ea44 ORR r5,r4,r5,LSR #16
;;;550
;;;551 /* Set the Capture Compare Register value */
;;;552 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
000282 88cc LDRH r4,[r1,#6]
000284 f8a0f8a0 STRH r4,[r0,#0x40]
;;;553
;;;554 if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
000288 4c5b LDR r4,|L1.1016|
00028a 42a0 CMP r0,r4
00028c d002 BEQ |L1.660|
00028e 4c5b LDR r4,|L1.1020|
000290 42a0 CMP r0,r4
000292 d105 BNE |L1.672|
|L1.660|
;;;555 {
;;;556 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;557
;;;558 /* Reset the Ouput Compare IDLE State */
;;;559 tmpcr2 &= CR2_OIS4_Reset;
000294 f3c2f3c2 UBFX r4,r2,#0,#14
;;;560
;;;561 /* Set the Output Idle state */
;;;562 tmpcr2 |= (u16)(TIM_OCInitStruct->TIM_OCIdleState << 6);
000298 8989 LDRH r1,[r1,#0xc]
00029a 0589 LSLS r1,r1,#22
00029c ea44ea44 ORR r2,r4,r1,LSR #16
|L1.672|
;;;563 }
;;;564
;;;565 /* Write to TIMx CR2 */
;;;566 TIMx->CR2 = tmpcr2;
0002a0 8082 STRH r2,[r0,#4]
;;;567
;;;568 /* Write to TIMx CCMR2 */
;;;569 TIMx->CCMR2 = tmpccmrx;
0002a2 8383 STRH r3,[r0,#0x1c]
;;;570
;;;571 /* Write to TIMx CCER */
;;;572 TIMx->CCER = tmpccer;
0002a4 8405 STRH r5,[r0,#0x20]
;;;573 }
0002a6 bd30 POP {r4,r5,pc}
;;;574
ENDP
TIM_SetIC4Prescaler PROC
;;;2758 /* Reset the IC4PSC Bits */
;;;2759 TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
0002a8 8b82 LDRH r2,[r0,#0x1c]
0002aa f422f422 BIC r2,r2,#0xc00
0002ae 8382 STRH r2,[r0,#0x1c]
;;;2760
;;;2761 /* Set the IC4PSC value */
;;;2762 TIMx->CCMR2 |= (u16)(TIM_ICPSC << 8);
0002b0 8b82 LDRH r2,[r0,#0x1c]
0002b2 ea42ea42 ORR r2,r2,r1,LSL #8
0002b6 8382 STRH r2,[r0,#0x1c]
;;;2763 }
0002b8 4770 BX lr
;;;2764
ENDP
TI4_Config PROC
;;;3198 u16 TIM_ICFilter)
;;;3199 {
0002ba b530 PUSH {r4,r5,lr}
;;;3200 u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
;;;3201
;;;3202 /* Disable the Channel 4: Reset the CC4E Bit */
;;;3203 TIMx->CCER &= CCER_CC4E_Reset;
0002bc 8c04 LDRH r4,[r0,#0x20]
0002be f424f424 BIC r4,r4,#0x1000
0002c2 8404 STRH r4,[r0,#0x20]
;;;3204
;;;3205 tmpccmr2 = TIMx->CCMR2;
0002c4 8b85 LDRH r5,[r0,#0x1c]
;;;3206 tmpccer = TIMx->CCER;
0002c6 8c04 LDRH r4,[r0,#0x20]
;;;3207 tmp = (u16)(TIM_ICPolarity << 12);
0002c8 0309 LSLS r1,r1,#12
;;;3208
;;;3209 /* Select the Input and set the filter */
;;;3210 tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
0002ca f425f425 BIC r5,r5,#0xf300
;;;3211 tmpccmr2 |= (u16)(TIM_ICSelection << 8) | (u16)(TIM_ICFilter << 12);
0002ce 0212 LSLS r2,r2,#8
0002d0 ea42ea42 ORR r2,r2,r3,LSL #12
0002d4 432a ORRS r2,r2,r5
;;;3212
;;;3213 /* Select the Polarity and set the CC4E Bit */
;;;3214 tmpccer &= CCER_CC4P_Reset;
0002d6 f424f424 BIC r3,r4,#0x2000
;;;3215 tmpccer |= tmp | CCER_CC4E_Set;
0002da 430b ORRS r3,r3,r1
0002dc f443f443 ORR r1,r3,#0x1000
;;;3216
;;;3217 /* Write to TIMx CCMR2 and CCER registers */
;;;3218 TIMx->CCMR2 = tmpccmr2;
0002e0 8382 STRH r2,[r0,#0x1c]
;;;3219 TIMx->CCER = tmpccer ;
0002e2 8401 STRH r1,[r0,#0x20]
;;;3220 }
0002e4 bd30 POP {r4,r5,pc}
;;;3221
ENDP
TIM_SetIC3Prescaler PROC
;;;2730 /* Reset the IC3PSC Bits */
;;;2731 TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
0002e6 8b82 LDRH r2,[r0,#0x1c]
0002e8 f022f022 BIC r2,r2,#0xc
0002ec 8382 STRH r2,[r0,#0x1c]
;;;2732
;;;2733 /* Set the IC3PSC value */
;;;2734 TIMx->CCMR2 |= TIM_ICPSC;
0002ee 8b82 LDRH r2,[r0,#0x1c]
0002f0 430a ORRS r2,r2,r1
0002f2 8382 STRH r2,[r0,#0x1c]
;;;2735 }
0002f4 4770 BX lr
;;;2736
ENDP
TI3_Config PROC
;;;3151 u16 TIM_ICFilter)
;;;3152 {
0002f6 b530 PUSH {r4,r5,lr}
;;;3153 u16 tmpccmr2 = 0, tmpccer = 0, tmp = 0;
;;;3154
;;;3155 /* Disable the Channel 3: Reset the CC3E Bit */
;;;3156 TIMx->CCER &= CCER_CC3E_Reset;
0002f8 8c04 LDRH r4,[r0,#0x20]
0002fa f424f424 BIC r4,r4,#0x100
0002fe 8404 STRH r4,[r0,#0x20]
;;;3157
;;;3158 tmpccmr2 = TIMx->CCMR2;
000300 8b85 LDRH r5,[r0,#0x1c]
;;;3159 tmpccer = TIMx->CCER;
000302 8c04 LDRH r4,[r0,#0x20]
;;;3160 tmp = (u16)(TIM_ICPolarity << 8);
000304 0209 LSLS r1,r1,#8
;;;3161
;;;3162 /* Select the Input and set the filter */
;;;3163 tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
000306 f025f025 BIC r5,r5,#0xf3
;;;3164 tmpccmr2 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4);
00030a ea42ea42 ORR r3,r2,r3,LSL #4
00030e 432b ORRS r3,r3,r5
;;;3165
;;;3166 /* Select the Polarity and set the CC3E Bit */
;;;3167 tmpccer &= CCER_CC3P_Reset;
000310 f424f424 BIC r2,r4,#0x200
;;;3168 tmpccer |= tmp | CCER_CC3E_Set;
000314 430a ORRS r2,r2,r1
000316 f442f442 ORR r1,r2,#0x100
;;;3169
;;;3170 /* Write to TIMx CCMR2 and CCER registers */
;;;3171 TIMx->CCMR2 = tmpccmr2;
00031a 8383 STRH r3,[r0,#0x1c]
;;;3172 TIMx->CCER = tmpccer;
00031c 8401 STRH r1,[r0,#0x20]
;;;3173 }
00031e bd30 POP {r4,r5,pc}
;;;3174
ENDP
TIM_SetIC2Prescaler PROC
;;;2702 /* Reset the IC2PSC Bits */
;;;2703 TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
000320 8b02 LDRH r2,[r0,#0x18]
000322 f422f422 BIC r2,r2,#0xc00
000326 8302 STRH r2,[r0,#0x18]
;;;2704
;;;2705 /* Set the IC2PSC value */
;;;2706 TIMx->CCMR1 |= (u16)(TIM_ICPSC << 8);
000328 8b02 LDRH r2,[r0,#0x18]
00032a ea42ea42 ORR r2,r2,r1,LSL #8
00032e 8302 STRH r2,[r0,#0x18]
;;;2707 }
000330 4770 BX lr
;;;2708
ENDP
TI2_Config PROC
;;;3103 u16 TIM_ICFilter)
;;;3104 {
000332 b530 PUSH {r4,r5,lr}
;;;3105 u16 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
;;;3106
;;;3107 /* Disable the Channel 2: Reset the CC2E Bit */
;;;3108 TIMx->CCER &= CCER_CC2E_Reset;
000334 8c04 LDRH r4,[r0,#0x20]
000336 f024f024 BIC r4,r4,#0x10
00033a 8404 STRH r4,[r0,#0x20]
;;;3109
;;;3110 tmpccmr1 = TIMx->CCMR1;
00033c 8b05 LDRH r5,[r0,#0x18]
;;;3111 tmpccer = TIMx->CCER;
00033e 8c04 LDRH r4,[r0,#0x20]
;;;3112 tmp = (u16)(TIM_ICPolarity << 4);
000340 0109 LSLS r1,r1,#4
;;;3113
;;;3114 /* Select the Input and set the filter */
;;;3115 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
000342 f425f425 BIC r5,r5,#0xf300
;;;3116 tmpccmr1 |= (u16)(TIM_ICFilter << 12);
000346 ea45ea45 ORR r3,r5,r3,LSL #12
;;;3117 tmpccmr1 |= (u16)(TIM_ICSelection << 8);
00034a ea43ea43 ORR r2,r3,r2,LSL #8
;;;3118
;;;3119 /* Select the Polarity and set the CC2E Bit */
;;;3120 tmpccer &= CCER_CC2P_Reset;
00034e f024f024 BIC r3,r4,#0x20
;;;3121 tmpccer |= tmp | CCER_CC2E_Set;
000352 430b ORRS r3,r3,r1
000354 f043f043 ORR r1,r3,#0x10
;;;3122
;;;3123 /* Write to TIMx CCMR1 and CCER registers */
;;;3124 TIMx->CCMR1 = tmpccmr1 ;
000358 8302 STRH r2,[r0,#0x18]
;;;3125 TIMx->CCER = tmpccer;
00035a 8401 STRH r1,[r0,#0x20]
;;;3126 }
00035c bd30 POP {r4,r5,pc}
;;;3127
ENDP
TIM_SetIC1Prescaler PROC
;;;2674 /* Reset the IC1PSC Bits */
;;;2675 TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
00035e 8b02 LDRH r2,[r0,#0x18]
000360 f022f022 BIC r2,r2,#0xc
000364 8302 STRH r2,[r0,#0x18]
;;;2676
;;;2677 /* Set the IC1PSC value */
;;;2678 TIMx->CCMR1 |= TIM_ICPSC;
000366 8b02 LDRH r2,[r0,#0x18]
000368 430a ORRS r2,r2,r1
00036a 8302 STRH r2,[r0,#0x18]
;;;2679 }
00036c 4770 BX lr
;;;2680
ENDP
TI1_Config PROC
;;;3057 u16 TIM_ICFilter)
;;;3058 {
00036e b530 PUSH {r4,r5,lr}
;;;3059 u16 tmpccmr1 = 0, tmpccer = 0;
;;;3060
;;;3061 /* Disable the Channel 1: Reset the CC1E Bit */
;;;3062 TIMx->CCER &= CCER_CC1E_Reset;
000370 8c04 LDRH r4,[r0,#0x20]
000372 f024f024 BIC r4,r4,#1
000376 8404 STRH r4,[r0,#0x20]
;;;3063
;;;3064 tmpccmr1 = TIMx->CCMR1;
000378 8b05 LDRH r5,[r0,#0x18]
;;;3065 tmpccer = TIMx->CCER;
00037a 8c04 LDRH r4,[r0,#0x20]
;;;3066
;;;3067 /* Select the Input and set the filter */
;;;3068 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
00037c f025f025 BIC r5,r5,#0xf3
;;;3069 tmpccmr1 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4);
000380 ea42ea42 ORR r3,r2,r3,LSL #4
000384 432b ORRS r3,r3,r5
;;;3070
;;;3071 /* Select the Polarity and set the CC1E Bit */
;;;3072 tmpccer &= CCER_CC1P_Reset;
000386 f024f024 BIC r2,r4,#2
;;;3073 tmpccer |= TIM_ICPolarity | CCER_CC1E_Set;
00038a 430a ORRS r2,r2,r1
00038c f042f042 ORR r1,r2,#1
;;;3074
;;;3075 /* Write to TIMx CCMR1 and CCER registers */
;;;3076 TIMx->CCMR1 = tmpccmr1;
000390 8303 STRH r3,[r0,#0x18]
;;;3077 TIMx->CCER = tmpccer;
000392 8401 STRH r1,[r0,#0x20]
;;;3078 }
000394 bd30 POP {r4,r5,pc}
;;;3079
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